Chapter 9 Memory Diagnosis and BuiltIn Self Repair
Chapter 9 Memory Diagnosis and Built-In Self -Repair EE 141 VLSI Test Principles and Architectures 1 Ch. 9 - Memory Diagnosis & BISR -
What is this chapter about? q Why diagnostics? § Yield improvement – Repair and/or design/process debugging q BIST design with diagnosis support q MECA: a system for automatic identification of fault site and fault type q Built-in self-repair (BISR) for embedded memories § Redundancy analysis (RA) algorithms § Built-in redundancy analysis (BIRA) EE 141 VLSI Test Principles and Architectures 2 Ch. 9 - Memory Diagnosis & BISR -
How to Identify Faults? RAM Circuit/Layout EE 141 VLSI Test Principles and Architectures Tester/BIST Output 3 Ch. 9 - Memory Diagnosis & BISR -
Fault Model Subtypes EE 141 VLSI Test Principles and Architectures 4 Ch. 9 - Memory Diagnosis & BISR -
March Signature & Dictionary March 11 N E 0 E 1 E 2 E 3 E 4 E 5 EE 141 VLSI Test Principles and Architectures E 6 E 7 E 8 E 9 E 10 5 Ch. 9 - Memory Diagnosis & BISR -
(MECA) Source: Wu, et al. , ICCAD 00 EE 141 VLSI Test Principles and Architectures 6 Ch. 9 - Memory Diagnosis & BISR -
BIST with Diagnosis Support EE 141 VLSI Test Principles and Architectures Source: Wang, et al. , ATS 00 7 Ch. 9 - Memory Diagnosis & BISR -
Test Mode q In Test Mode it runs a fixed algorithm for production test and repair. § Only a few pins need to be controlled, and BGO reports the result (Go/No-Go). EE 141 VLSI Test Principles and Architectures 8 Ch. 9 - Memory Diagnosis & BISR -
CTR State Diagram in Test Mode EE 141 VLSI Test Principles and Architectures 9 Ch. 9 - Memory Diagnosis & BISR -
Fault Analysis Mode (FSI Timing) q In Fault Analysis Mode, we can apply a longer March algorithm for diagnosis § FSI captures the error information of the faulty cells EOP format: EE 141 VLSI Test Principles and Architectures 10 Ch. 9 - Memory Diagnosis & BISR -
CTR State Diagram in Analysis Mode EE 141 VLSI Test Principles and Architectures 11 Ch. 9 - Memory Diagnosis & BISR -
Fault Analysis q Derive analysis equations from the fault dictionary · Convert error maps to fault maps by the equations EE 141 VLSI Test Principles and Architectures 12 Ch. 9 - Memory Diagnosis & BISR -
TPG State Diagram EE 141 VLSI Test Principles and Architectures 13 Ch. 9 - Memory Diagnosis & BISR -
Waveform Generated by TPG EE 141 VLSI Test Principles and Architectures 14 Ch. 9 - Memory Diagnosis & BISR -
Diagnostic Test Algorithm Generation q q q Start from a base test: generated by TAGS, or user-specified Generation options reduced to Read insertions Diagnostic resolution: percentage of faults that can be distinguished EE 141 VLSI Test Principles and Architectures 15 Ch. 9 - Memory Diagnosis & BISR -
Fault Bitmap Examples Idempotent Coupling Fault EE 141 VLSI Test Principles and Architectures Stuck-at 0 16 Ch. 9 - Memory Diagnosis & BISR -
Redundancy and Repair q Problem: § We keep shrinking RAM cell size and increasing RAM density and capacity. How do we maintain the yield? q Solutions: § Fabrication – Material, process, equipment, etc. § Design – Device, circuit, etc. § Redundancy and repair – On-line l EDAC (extended Hamming code; product code) – Off-line l Spare rows, columns, blocks, etc. EE 141 VLSI Test Principles and Architectures 17 Ch. 9 - Memory Diagnosis & BISR -
From BIST to BISR BIST BISD BIRA BISR • BIST: built-in self-test • BIECA: built-in error catch & analysis -BISD: built-in self diagnosis -BIRA: built-in redundancy analysis • BISR: built-in self-repair EE 141 VLSI Test Principles and Architectures 18 Ch. 9 - Memory Diagnosis & BISR -
RAM Built-In Self-Repair (BISR) Reconfiguration Mechanism Analyzer MUX RAM Spare Elements Redundancy BIST EE 141 VLSI Test Principles and Architectures 19 Ch. 9 - Memory Diagnosis & BISR -
RAM Redundancy Allocation q 1 -D: spare rows (or columns) only § SRAM § Algorithm: Must-Repair q 2 -D: spare rows and columns (or blocks) § Local and/or global spares § NP-complete problem § Conventional algorithm: – Must-Repair phase – Final-Repair phase l l l Repair-Most (greedy) [Tarr et al. , 1984] Fault-Driven (exhaustive, slow) [Day, 1985] Fault-Line Covering (b&b) [Huang et al. , 1990] EE 141 VLSI Test Principles and Architectures 20 Ch. 9 - Memory Diagnosis & BISR -
Redundancy Architectures EE 141 VLSI Test Principles and Architectures 21 Ch. 9 - Memory Diagnosis & BISR -
Redundancy Analysis Simulation Memory Defect Injection Fault Translation Faulty Memory Test Algorithm Simulation RA Algorithm Fail bit map and sub-maps Spare Elements RA Simulation Result Ref: MTDT 02 EE 141 VLSI Test Principles and Architectures 22 Ch. 9 - Memory Diagnosis & BISR -
Definitions q Faulty line: row or column with at least one faulty cell § A faulty line is covered if all faulty cells in the line are repaired by spare rows and/or columns. A faulty cell not sharing any row or column with any other faulty cell is an orthogonal faulty cell q r: number of (available) spare rows q c: number of (available) spare columns q F: number of faulty cells in a block q F’: number of orthogonal faulty cells in a block q EE 141 VLSI Test Principles and Architectures 23 Ch. 9 - Memory Diagnosis & BISR -
Example Block with Faulty Cells EE 141 VLSI Test Principles and Architectures 24 Ch. 9 - Memory Diagnosis & BISR -
Repair-Most (RM) 1. Run BIST and construct bitmap 2. Construct row and column error counters 3. Run Must-Repair algorithm 4. Run greedy final-repair algorithm EE 141 VLSI Test Principles and Architectures 25 Ch. 9 - Memory Diagnosis & BISR -
Repair) • Max F=2 rc • Max F’=r+c • Bitmap size: (rc+c)(cr+r) r=2; c=4 EE 141 VLSI Test Principles and Architectures 26 Ch. 9 - Memory Diagnosis & BISR -
Essential Spare Pivoting (ESP) q Maintain high repair rate without using a bitmap § Small area overhead q Fault Collection (FC) § Collect and store faulty-cell address using rowpivot and column-pivot registers – If there is a match for row (col) pivot, the pivot is an essential pivot – If there is no match, store the row/col addresses in the pivot registers § If F > r+c, the RAM is irreparable q Spare Allocation (SA) § Use row and column pivots for spare allocation – Spare rows (cols) for essential row (col) pivots § SA for orthogonal faults EE 141 VLSI Test Principles and Architectures Ref: Huang et al. , IEEE TR, 11/03 27 Ch. 9 - Memory Diagnosis & BISR -
ESP Example (1, 0) (1, 6) (2, 4) EE 141 VLSI Test Principles and Architectures (3, 4) (5, 1) (5, 2) (7, 3) 28 Ch. 9 - Memory Diagnosis & BISR -
Cell Fault Size Distribution Mixed Poisson-exponential distribution EE 141 VLSI Test Principles and Architectures 29 Ch. 9 - Memory Diagnosis & BISR -
Repair Rate (r=10) EE 141 VLSI Test Principles and Architectures 30 Ch. 9 - Memory Diagnosis & BISR -
Redundancy Organization SEG 0 SEG 1 SR: Spare Row; SCG: Spare Column Group; SEG: Segment EE 141 VLSI Test Principles and Architectures SCG 1 SCG 0 SR 1 ITC 03 31 Ch. 9 - Memory Diagnosis & BISR -
BISR Architecture Q D MAO BIRA POR BIST Wrapper A Main Memory Spare Memory MAO: mask address output; POR: power-on reset EE 141 VLSI Test Principles and Architectures Ref: ITC 03 32 Ch. 9 - Memory Diagnosis & BISR -
Power-On BISR Procedure EE 141 VLSI Test Principles and Architectures 33 Ch. 9 - Memory Diagnosis & BISR -
Subword Definition q Subword § A subword is consecutive bits of a word. § Its length is the same as the group size. q Example: a 32 x 16 RAM with 3 -bit row address and 2 -bit column address A word with 4 subwords A subword with 4 bits EE 141 VLSI Test Principles and Architectures 34 Ch. 9 - Memory Diagnosis & BISR -
Row-Repair Rules q To reduce the complexity, we use two row-repair rules § If a row has multiple faulty, we repair the faulty row by a spare row if available. § If there are multiple faulty subwords with the same column address and different row addresses within a segment, the last detected faulty subword should be repaired with an available spare row. q Examples: subword EE 141 VLSI Test Principles and Architectures subword 35 Ch. 9 - Memory Diagnosis & BISR -
BIRA Procedure EE 141 VLSI Test Principles and Architectures 36 Ch. 9 - Memory Diagnosis & BISR -
Basic BIST Module EE 141 VLSI Test Principles and Architectures 37 Ch. 9 - Memory Diagnosis & BISR -
BIRA Module EE 141 VLSI Test Principles and Architectures 38 Ch. 9 - Memory Diagnosis & BISR -
State Diagram of PE EE 141 VLSI Test Principles and Architectures 39 Ch. 9 - Memory Diagnosis & BISR -
Block Diagram of ARU EE 141 VLSI Test Principles and Architectures 40 Ch. 9 - Memory Diagnosis & BISR -
Repair Rate Analysis q Repair rate § The ratio of the number of repaired memories to the number of defective memories q A simulator has been implemented to estimate the repair rate of the proposed BISR scheme [Huang et al. , MTDT 02] q Industrial case: § § SRAM size: 8 Kx 64 # of injected random faults: 1~10 # of memory samples: 534 RA algorithms: proposed and exhaustive search algorithms EE 141 VLSI Test Principles and Architectures 41 Ch. 9 - Memory Diagnosis & BISR -
An Industrial Case EE 141 VLSI Test Principles and Architectures 42 Ch. 9 - Memory Diagnosis & BISR -
A 8 Kx 64 Repairable SRAM Technology: 0. 25 um SRAM area: 6. 5 mm 2 BISR area : 0. 3 mm 2 Spare area : 0. 3 mm 2 HOspare: 4. 6% HObisr: 4. 6% Repair rate: 100% (if # random faults is no more than 10) Redundancy: 4 spare rows and 2 spare column groups Group size: 4 EE 141 VLSI Test Principles and Architectures 43 Ch. 9 - Memory Diagnosis & BISR -
Waveform of EMA & MAO EE 141 VLSI Test Principles and Architectures 44 Ch. 9 - Memory Diagnosis & BISR -
Normal Mode Waveform EE 141 VLSI Test Principles and Architectures 45 Ch. 9 - Memory Diagnosis & BISR -
Repair Rate (Group Size 2) EE 141 VLSI Test Principles and Architectures 46 Ch. 9 - Memory Diagnosis & BISR -
Repair Rate (Group Size 4) EE 141 VLSI Test Principles and Architectures 47 Ch. 9 - Memory Diagnosis & BISR -
Yield vs. Repair Rate EE 141 VLSI Test Principles and Architectures 48 Ch. 9 - Memory Diagnosis & BISR -
Concluding Remarks q BIST with diagnosis support § Fault type identification done by an offline diagnosis process using MECA § RAM design and process debugging for yield enhancement q From BIST to BIRA § Effective implementation by ESP – Greedy algorithm q An industrial case has been experimented § Full repair achieved (for # random faults no more than 10) § Only 4. 6% area overhead for the 8 Kx 64 SRAM EE 141 VLSI Test Principles and Architectures 49 Ch. 9 - Memory Diagnosis & BISR -
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