Chapter 9 Design Constraints and Optimization 1 Overview

Chapter 9 Design Constraints and Optimization 1

Overview n Constraints are used to influence n n n Synthesizer tool Place-and-route tool The four primary types of constraints n n Synthesis I/O Timing Area/Location 2

Overview n Synthesis n n I/O constraints n n n How the synthesis of HDL code to RTL occurs Assign a signal to a specific I/O (pin) or I/O bank Timing constraints Area/Location 3

Design Constraint Management n Constraint implementation issue n n The wide range of potential configuration overlap and interference Effective design constraint implementation requires n A solid knowledge and understanding of both the system requirements and the current design implementation approach 4

Synthesis Constraints n n Synthesis constraints are used to direct the synthesis tool to perform specific operation Two important synthesis constraints n n REGISTER_BALANCING INCREMENTAL_SYNTHESIS n Reduce the total time it take to compile the design 5

XST Synthesis Constraints 6

Pin Constraints n Effective pin assignment requires detailed system-level design knowledge, including n n Board-level component relationships and interface details Targeted FPGA architecture details and proposed FPGA-level design implementation 7

FPGA Clock Design Guidelines n n Separate FPGA clocks into priority groups Assign the highest priority clocks first Assign clock block management resources Manage lower priority clocks 8

Timing Constraints n n Identify and constrain system clocks Identify and create signal path groups Assign global constraints Assign detailed group and individual path constraints 9

Input Timing Constraint 10

Output Timing Constraint 11

Area Constraints and Floorplanning n Area constraints may also define a potential placement region for design elements 12

Design Optimization 13

Q&A 14