Chapter 8 Overview Programmed IO Introduction to Interrupt

Chapter 8 Overview • Programmed I/O • Introduction to Interrupt Driven I/O Project 3

Digressing How do you do the following in the LC-3 ? (good test question ? ) • Shift left • Rotate left • Shift right • Rotate right

Input / Output Memory Mapped I/O – A section of the memory address space is reserved for I/O Registers rather than general memory locations. Think of it as “pseudo” memory. The same instructions are used for general programming and I/O programming. Non-Memory Mapped I/O – There is a separate address space for I/O programming, and an entirely separate set of I/O Instructions.

LC-3 has Memory Mapped I/O LC-3 Memory Layout: x 0000 – x 00 FF Trap vectors x 0100 – x 2 FFF System Programs & Data x 3000 – x. FDFF User Programs Area x. FE 00 – x. FFFF I/O Programming “Registers”

LC-3 has Memory Mapped I/O LC-3 Memory Layout: x 0000 – x 00 FF Trap vectors (Supports Software Interrupts) x 0020 [x 0400] GETC (Read Char from Keyboard) x 0021 [x 0430] OUT x 0022 [x 0450] PUTS (Write string to Console) x 0023 [x 04 A 0] IN x 0024 [x 04 E 0] PUTSP (Write “packed” string to Console) x 0025 [x. FD 70] HALT (Turn off run latch in MCR) x 0100 – x 01 FF (Write Character to Console) (Prompt, input character from Keyboard, echo character to Console) Interrupt Vectors (Supports Hardware Interrupts) x 0200 – x 2 FFF System Programs & Data (“Operating System”) x 3000 – x. FDFF User Programs Area x. FE 00 – x. FFFF I/O Programming “Registers” (Mapped I/O Regs) x. FE 00 KBSR [15 {Ready}, 14 {Intr enable}] (Keyboard Status Register) x. FE 02 KBDR [7: 0{ascii data}] (Keyboard Data Register) x. FE 04 DSR [15{Done}, 14{Intr enable}] (Display Status Register) x. FE 06 DDR [7: 0{ascii data}] x. FFFE MCR [15{Run latch}] (Display Data Register (Machine Control Register)

Synchronous vs Asynchronous I/O Synchronous – latest value of data could be expected to be available when the program wanted it. It might be periodically updated at a know frequency. This is not typical nor usually realistic for I/O. Asynchronous – computer is generally much faster than I/O so program must wait until requested data is available or data provided has been taken. “Handshaking” is used to ensure that data is available or I/O device is ready.

Polling vs Interrrupt Driven I/O Polling – program checks handshaking signals to find when data is available of device is done (typically a loop in the program) Interrupt – program initiates I/O and waits until data is available (typically goes to sleep until the operating system wakes the program up)

Keyboard Input Interface

Keyboard Input Registers KBDR (Keyboard Data Register): Assigned to x. FE 02 Data is in KBDR[7: 0] Read only Register KBSR (Keyboard Status Register): Assigned to x. FE 00 Status “ready” is KBSR[15] Set to “ 1” when new data is ready Cleared when data is read

Simple Program for Input from Keyboard ; Waiting for a character to be entered START LDI R 1, KBSR ; Test for character input BRzp START ; LDI R 0, KBDR ; Read character BRnzp NEXT_TASK ; Go to the next task KBSR . FILL x. FE 00 ; Address of KBSR (Keyboard Status Register) KBDR . FILL x. FE 02 ; Address of KBDR (Keyboard Data Register) If not there, try again

Console Output Interface

Console (Monitor) Output Registers DDR (Data Direction Register): Assigned to Address x. FE 06 Data is in DDR[7: 0] DSR (Data Register): Assigned to Address x. FE 04 Status “done” bit is DSR[15] Set to “ 1” when data is picked up Cleared when new data is written

Simple Program to Output to Console (Monitor) ; Wait for write to Console done START LDI R 1, DSR ; Test for output written BRzp START ; STI R 0, DDR ; Write character BRnzp NEXT_TASK ; Go to next task DSR . FILL x. FE 04 ; Address of DSR (Display Status Register) DDR . FILL x. FE 06 ; Address of DDR (Display Data Register) If not, try again

LC-3 Memory Mapped I/O

Echo from Keyboard to Monitor ; Echo keyboard input to Console output START ECHO LDI R 1, KBSR BRzp START LDI R 0, KBDR LDI R 1, DSR BRzp ECHO STI R 0, DDR ; Test for input ready ; Test for output done BRnzp NEXT_TASK KBSR . FILL x. FE 00 ; Address of KBSR KBDR . FILL x. FE 02 ; Address of KBDR DSR . FILL x. FE 04 ; Address of DSR DDR . FILL x. FE 06 ; Address of DDR

The I/O Routine to Echo a Line of Input. orig x 3000 ; Program to read and echo line from the Console L 1 Loop L 2 ST ST ST R 1, Save. R 1 R 2, Save. R 2 R 3, Save. R 3 ; Save registers needed ; by this routine LD R 2, Newline ; Store newline Character in R 2 LDI BRzp STI R 3, DSR L 1 R 2, DDR ; Loop until Monitor is done LEA LDR BRz R 1, Prompt R 0, R 1, #0 Input ; Load starting address of prompt string ; Get prompt character ; Branch to Loop on null (0) LDI BRzp STI ADD BRnzp R 3, DSR L 2 R 0, DDR R 1, #1 Loop ; Loop until Monitor is done ; Move cursor to new clean line ; Write prompt character ; Increment Prompt pointer ; Go to get next prompt character

The I/O Routine to Echo a Line of Input (2) Input L 3 L 4 LDI BRzp LDI R 3, KBSR Input R 0, KBDR ; Poll until a character is typed LDI BRzp STI R 3, DSR L 3 R 0, DDR ; Loop until Monitor is done ADD BRnp R 0, #-10 ; Test for newline (done) Input ; Loop if not done LDI BRzp STI R 3, DSR L 4 R 2, DDR ; Loop until Monitor is done LD LD LD R 1, Save. R 1 R 2, Save. R 2 R 3, Save. R 3 ; Restore registers ; to original values BRnzp NEXT_TASK ; Do the program's next task ; ; ; Get input character Echo input character Move cursor to new clean line

The I/O Routine to Echo a Line of Input (3) Save. R 1 Save. R 2 Save. R 3 . BLKW 1 1 1 DSR DDR KBSR KBDR . FILL x. FE 04 x. FE 06 x. FE 00 x. FE 02 Newline. FILL x 000 A Prompt ; Memory for registers saved ; ASCII code for newline . STRINGZ "Input character line> " NEXT_TASK BRnzp NEXT_TASK. END Run on Simulator ; Simulates next task

I/O Interrupts Requirements for a device to interrupt the processor • The device must have the right to request service • The I/O device must want service • The device request must be at a higher priority than what is being done by the processor or is being requested by other devices • The processor must be completed with the present instruction execution

Device(s) Generating Interrupt Request

Generating the LC-3 Interrupt Request

Servicing an Interrupt The following process is followed to service an interrupt • The CPU enters the Supervisor State • The “context” of the present program is saved (PC, PSW, SP) • The device provides the address of location in the interrupt service routine table where the pointer to the service routine should reside. • The Supervisor loads the address of the service routine into the PC • The service routine is executed (ending with an RTI) • The context of the original program is loaded and the original program resumed