Chapter 8 Memory Management Chapter 8 Memory Management
- Slides: 61
Chapter 8: Memory Management
Chapter 8: Memory Management n Background n Swapping n Contiguous Allocation n Paging n Segmentation with Paging Operating System Concepts 8. 2 Silberschatz, Galvin and Gagne © 2005
Background n Program must be brought into memory and placed within a process for it to be run n Input queue – collection of processes on the disk that are waiting to be brought into memory to run the program n User programs go through several steps before being run Operating System Concepts 8. 3 Silberschatz, Galvin and Gagne © 2005
Binding of Instructions and Data to Memory Address binding of instructions and data to memory addresses can happen at three different stages n Compile time: If memory location known a priori, absolute code can be generated; must recompile code if starting location changes n Load time: Must generate relocatable code if memory location is not known at compile time n Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another. Need hardware support for address maps (e. g. , base and limit registers). Operating System Concepts 8. 4 Silberschatz, Galvin and Gagne © 2005
Step on Executing Code Compile >gcc first. c >g++ first. c a. out pertamax. out >gcc -o pertamax first. c Run >. /pertamax #first. c #include <stdio. h> int main(void) { printf("My first C programn"); return 0; } Operating System Concepts 8. 5 Silberschatz, Galvin and Gagne © 2005
Multistep Processing of a User Program Operating System Concepts 8. 6 Silberschatz, Galvin and Gagne © 2005
System Library n System libraries are special functions or programs using which application programs or system utilities accesses Kernel's features. n These libraries implements most of the functionalities of the operating system and do not requires kernel module's code access rights. n In linux, it is saved in /lib , /usr/local/lib or /usr/lib and saved as file with so extension n In Windows, it is file with dll extension Operating System Concepts 8. 7 Silberschatz, Galvin and Gagne © 2005
Logical vs. Physical Address Space n The concept of a logical address space that is bound to a separate physical address space is central to proper memory management l Logical address – generated by the CPU; also referred to as virtual address l Physical address – address seen by the memory unit n Logical and physical addresses are the same in compile-time and load-time address-binding schemes; n Logical (virtual) and physical addresses differ in execution-time address-binding scheme Operating System Concepts 8. 8 Silberschatz, Galvin and Gagne © 2005
Memory-Management Unit (MMU) n Hardware device that maps virtual to physical address n In MMU scheme, the value in the relocation register is added to every address generated by a user process at the time it is sent to memory n The user program deals with logical addresses; it never sees the real physical addresses Operating System Concepts 8. 9 Silberschatz, Galvin and Gagne © 2005
Dynamic relocation using a relocation register Operating System Concepts 8. 10 Silberschatz, Galvin and Gagne © 2005
Dynamic Loading n Routine is not loaded until it is called. Routine can be a procedure or task performed by system n Better memory-space utilization; unused routine is never loaded n Useful when large amounts of code are needed to handle infrequently occurring cases n No special support from the operating system is required implemented through program design Operating System Concepts 8. 11 Silberschatz, Galvin and Gagne © 2005
Dynamic Linking n Linking postponed until execution time n Small piece of code, stub, used to locate the appropriate memory-resident library routine n Stub replaces itself with the address of the routine, and executes the routine n Operating system needed to check if routine is in processes’ memory address n Dynamic linking is particularly useful for libraries Operating System Concepts 8. 12 Silberschatz, Galvin and Gagne © 2005
Swapping n A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution n Backing store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images n Roll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed n Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped n Modified versions of swapping are found on many systems (i. e. , UNIX, Linux, and Windows) Operating System Concepts 8. 13 Silberschatz, Galvin and Gagne © 2005
Swapping Action n xx Secondary memory acts as backing store Operating System Concepts 8. 14 Silberschatz, Galvin and Gagne © 2005
Contiguous Allocation n Main memory usually into two partitions: l Resident operating system, usually held in low memory with interrupt vector l n User processes then held in high memory Single-partition allocation l Relocation-register scheme used to protect user processes from each other, and from changing operating-system code and data l Relocation register contains value of smallest physical address; limit register contains range of logical addresses – each logical address must be less than the limit register Operating System Concepts 8. 15 Silberschatz, Galvin and Gagne © 2005
A base and a limit register define a logical address space Operating System Concepts 8. 16 Silberschatz, Galvin and Gagne © 2005
HW address protection with base and limit registers Operating System Concepts 8. 17 Silberschatz, Galvin and Gagne © 2005
Contiguous Allocation (Cont. ) n Multiple-partition allocation l Hole – block of available memory; holes of various size are scattered throughout memory l When a process arrives, it is allocated memory from a hole large enough to accommodate it l Operating system maintains information about: a) allocated partitions b) free partitions (hole) OS OS process 5 process 9 process 8 process 2 Operating System Concepts process 10 process 2 8. 18 process 2 Silberschatz, Galvin and Gagne © 2005
Dynamic Storage-Allocation Problem How to satisfy a request of size n from a list of free holes n First-fit: Allocate the first hole that is big enough n Best-fit: Allocate the smallest hole that is big enough; must search entire list, unless ordered by size. Produces the smallest leftover hole. n Worst-fit: Allocate the largest hole; must also search entire list. Produces the largest leftover hole. First-fit and best-fit better than worst-fit in terms of speed and storage utilization Operating System Concepts 8. 19 Silberschatz, Galvin and Gagne © 2005
Fragmentation q Fragmentation is a phenomenon in which storage space is used inefficiently, reducing capacity or performance and often both. q Internal & External Fragmentation q Solution : q Reduce external fragmentation by compaction q Shuffle memory contents to place all free memory together in one large block q Compaction is possible only if relocation is dynamic, and is done at execution time q I/O problem q Latch job in memory while it is involved in I/O q Do I/O only into OS buffers Operating System Concepts 8. 20 Silberschatz, Galvin and Gagne © 2005
External and Internal fragmentation n External Fragmentation – total memory space exists to satisfy a request, but it is not contiguous n Internal Fragmentation – allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used Operating System Concepts 8. 21 Silberschatz, Galvin and Gagne © 2005
Compaction Operating System Concepts 8. 22 Silberschatz, Galvin and Gagne © 2005
Paging q Logical address space of a process can be noncontiguous; process is allocated physical memory whenever the latter is available q Divide physical memory into fixed-sized blocks called frames (size is power of 2, between 512 bytes and 8192 bytes) q Divide logical memory into blocks of same size called pages. q Keep track of all free frames q To run a program of size n pages, need to find n free frames and load program q Set up a page table to translate logical to physical addresses q Internal fragmentation Operating System Concepts 8. 23 Silberschatz, Galvin and Gagne © 2005
Address Translation Scheme n Address generated by CPU is divided into: l Page number (p) – used as an index into a page table which contains base address of each page in physical memory l Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit Operating System Concepts 8. 24 Silberschatz, Galvin and Gagne © 2005
Example n Q: l n A computer uses 32 -bit byte addressing. The computer uses paged virtual memory with 4 KB pages. Calculate the number of bits in the page number and offset fields of a logical address. A l Since there are 4 K bytes in a cache block, the offset field must contain 12 bits (212 = 4 K). The remaining 20 bits are page number bits. l Thus a logical address is decomposed as shown below. Operating System Concepts 8. 25 Silberschatz, Galvin and Gagne © 2005
Address Translation Architecture Operating System Concepts 8. 26 Silberschatz, Galvin and Gagne © 2005
Paging Example Operating System Concepts 8. 27 Silberschatz, Galvin and Gagne © 2005
Paging Example Operating System Concepts 8. 28 Silberschatz, Galvin and Gagne © 2005
Free Frames Before allocation Operating System Concepts After allocation 8. 29 Silberschatz, Galvin and Gagne © 2005
Implementation of Page Table n Page table is kept in main memory n Page-table base register (PTBR) points to the page table n Page-table length register (PRLR) indicates size of the page table n In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction. n The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs) Operating System Concepts 8. 30 Silberschatz, Galvin and Gagne © 2005
Associative Memory q Associative memory – parallel search Page # Frame # q Located inside TLB. q Address translation (A´, A´´) § If A´ is in associative register, get frame # out § Otherwise get frame # from page table in memory Operating System Concepts 8. 31 Silberschatz, Galvin and Gagne © 2005
Paging Hardware With TLB Operating System Concepts 8. 32 Silberschatz, Galvin and Gagne © 2005
Effective Access Time n Associative Lookup = time unit n Assume memory cycle time is 1 microsecond n Hit ratio – percentage of times that a page number is found in the associative registers; ration related to number of associative registers n Hit ratio = n Effective Access Time (EAT) EAT = (1 + ) + (2 + )(1 – ) =2+ – Operating System Concepts 8. 33 Silberschatz, Galvin and Gagne © 2005
Memory Protection q Memory protection implemented by associating protection bit with each frame q Valid-invalid bit attached to each entry in the page table: § “valid” indicates that the associated page is in the process’ logical address space, and is thus a legal page § “invalid” indicates that the page is not in the process’ logical address space Operating System Concepts 8. 34 Silberschatz, Galvin and Gagne © 2005
Valid (v) or Invalid (i) Bit In A Page Table Operating System Concepts 8. 35 Silberschatz, Galvin and Gagne © 2005
Page Table Structure n Hierarchical Paging n Hashed Page Tables n Inverted Page Tables Operating System Concepts 8. 36 Silberschatz, Galvin and Gagne © 2005
Hierarchical Page Tables n Break up the logical address space into multiple page tables n A simple technique is a two-level page table Operating System Concepts 8. 37 Silberschatz, Galvin and Gagne © 2005
Two-Level Paging Example n A logical address (on 32 -bit machine with 4 K page size) is divided into: l a page number consisting of 20 bits a page offset consisting of 12 bits Since the page table is paged, the page number is further divided into: l a 10 -bit page number l n a 10 -bit page offset Thus, a logical address is as follows: l n page number pi 10 page offset p 2 d 10 12 where pi is an index into the outer page table, and p 2 is the displacement within the page of the outer page table Operating System Concepts 8. 38 Silberschatz, Galvin and Gagne © 2005
Two-Level Page-Table Scheme Operating System Concepts 8. 39 Silberschatz, Galvin and Gagne © 2005
Address-Translation Scheme n Address-translation scheme for a two-level 32 -bit paging architecture Operating System Concepts 8. 40 Silberschatz, Galvin and Gagne © 2005
Shared Pages n n Shared code l One copy of read-only (reentrant) code shared among processes (i. e. , text editors, compilers, window systems). l Shared code must appear in same location in the logical address space of all processes Private code and data l Each process keeps a separate copy of the code and data l The pages for the private code and data can appear anywhere in the logical address space Operating System Concepts 8. 41 Silberschatz, Galvin and Gagne © 2005
Shared Pages Example Operating System Concepts 8. 42 Silberschatz, Galvin and Gagne © 2005
Segmentation n Memory-management scheme that supports user view of memory n A program is a collection of segments. A segment is a logical unit such as: main program, procedure, function, method, object, local variables, global variables, common block, stack, symbol table, arrays Operating System Concepts 8. 43 Silberschatz, Galvin and Gagne © 2005
User’s View of a Program Operating System Concepts 8. 44 Silberschatz, Galvin and Gagne © 2005
Logical View of Segmentation 1 4 1 2 3 2 4 3 user space Operating System Concepts physical memory space 8. 45 Silberschatz, Galvin and Gagne © 2005
Segmentation Architecture n Logical address consists of a two tuple: <segment-number, offset>, n Segment table – maps two-dimensional physical addresses; each table entry has: l base – contains the starting physical address where the segments reside in memory l limit – specifies the length of the segment n Segment-table base register (STBR) points to the segment table’s location in memory n Segment-table length register (STLR) indicates number of segments used by a program; segment number s is legal if s < STLR Operating System Concepts 8. 46 Silberschatz, Galvin and Gagne © 2005
Segmentation Architecture (Cont. ) n n n Relocation. l dynamic l by segment table Sharing. l shared segments l same segment number Allocation. l first fit/best fit l external fragmentation Operating System Concepts 8. 47 Silberschatz, Galvin and Gagne © 2005
Segmentation Architecture (Cont. ) n Protection. With each entry in segment table associate: l validation bit = 0 illegal segment l read/write/execute privileges n Protection bits associated with segments; code sharing occurs at segment level n Since segments vary in length, memory allocation is a dynamic storage-allocation problem n A segmentation example is shown in the following diagram Operating System Concepts 8. 48 Silberschatz, Galvin and Gagne © 2005
Address Translation Architecture Operating System Concepts 8. 49 Silberschatz, Galvin and Gagne © 2005
Example of Segmentation Operating System Concepts 8. 50 Silberschatz, Galvin and Gagne © 2005
Sharing of Segments Operating System Concepts 8. 51 Silberschatz, Galvin and Gagne © 2005
Segmentation with Paging – MULTICS n The MULTICS system solved problems of external fragmentation and lengthy search times by paging the segments n Solution differs from pure segmentation in that the segment-table entry contains not the base address of the segment, but rather the base address of a page table for this segment Operating System Concepts 8. 52 Silberschatz, Galvin and Gagne © 2005
MULTICS Address Translation Scheme Operating System Concepts 8. 53 Silberschatz, Galvin and Gagne © 2005
Segmentation with Paging – Intel 386 n As shown in the following diagram, the Intel 386 uses segmentation with paging for memory management with a two-level paging scheme Operating System Concepts 8. 54 Silberschatz, Galvin and Gagne © 2005
Intel 30386 Address Translation Operating System Concepts 8. 55 Silberschatz, Galvin and Gagne © 2005
Linux on Intel 80 x 86 Uses minimal segmentation to keep memory management implementation more portable n Uses 6 segments: l Kernel code l Kernel data l User code (shared by all user processes, using logical addresses) l User data (likewise shared) l Task-state (per-process hardware context) l LDT n n Uses 2 protection levels: l Kernel mode l User mode Operating System Concepts 8. 56 Silberschatz, Galvin and Gagne © 2005
End of Chapter 8
Hashed Page Tables n Common in address spaces > 32 bits n The virtual page number is hashed into a page table. This page table contains a chain of elements hashing to the same location. n Virtual page numbers are compared in this chain searching for a match. If a match is found, the corresponding physical frame is extracted. Operating System Concepts 8. 58 Silberschatz, Galvin and Gagne © 2005
Hashed Page Table Operating System Concepts 8. 59 Silberschatz, Galvin and Gagne © 2005
Inverted Page Table n One entry for each real page of memory n Entry consists of the virtual address of the page stored in that real memory location, with information about the process that owns that page n Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs n Use hash table to limit the search to one — or at most a few — page-table entries Operating System Concepts 8. 60 Silberschatz, Galvin and Gagne © 2005
Inverted Page Table Architecture Operating System Concepts 8. 61 Silberschatz, Galvin and Gagne © 2005
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