Chapter 8 Main Memory Operating System Concepts 9

Objectives To provide a detailed description of various ways of organizing memory hardware To

Background Program must be brought (from disk) into memory and placed within a process

Base and Limit Registers A pair of base and limit registers define the logical

Hardware Address Protection Operating System Concepts – 9 th Edition 8. 5 Silberschatz, Galvin

Address representation Address are represented in different ways during different steps Source program: addresses

Binding of Instructions and Data to Memory Address binding of instructions and data to

Logical vs. Physical Address Space Logical address – generated by the CPU; also referred

Memory-Management Unit (MMU) Hardware device that at run time maps virtual to physical address

Dynamic relocation using a relocation register Dynamic relocation and Logical addresses benefits: Routine is

Schematic View of Swapping Operating System Concepts – 9 th Edition 8. 11 Silberschatz,

Memory allocation for process Fixed size Variable size Contiguous Allocation Causes p 0 Fixed

Fragmentation External Fragmentation – total memory space exists to satisfy a request, but it

Solution to Fragmentation problem Reduce external fragmentation by compaction Shuffle memory contents to place

Segmentation Memory-management scheme that supports user view of memory A program is a collection

User’s View of a Program Operating System Concepts – 9 th Edition 8. 16

Logical View of Segmentation 1 4 1 2 3 2 4 3 user space

Segmentation Architecture Logical address consists of a two tuple: <segment-number, offset>, Segment table –

Segmentation: Example What is the physical addresses of below logical addresses according to the

Paging Divide physical memory into fixed-sized blocks called frames Size is power of 2,

Address Translation Scheme Address generated by CPU is divided into: Page number (p) –

Paging Hardware Operating System Concepts – 9 th Edition 8. 22 Silberschatz, Galvin and

Paging Model of Logical and Physical Memory Operating System Concepts – 9 th Edition

Paging Example n=2 and m=4 32 -byte memory and 4 -byte pages Operating System

Paging: Example If the page size is equal to 1 KB, in logical address

Paging: Example There are 4 pages in a logical address space and each page

Paging (Cont. ) Calculating internal fragmentation Page size = 2, 048 bytes Process size

Implementation of Page Table Page table is kept in main memory Page-table base register

Increasing or Decreasing page size What is the benefits of increasing page size? In

Paging and segmentation Combination What if paging and segmentation used simultaneously? What is the

End of Chapter 8 Operating System Concepts – 9 th Edition Silberschatz, Galvin and

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Objectives To provide a detailed description of various ways of organizing memory hardware To discuss various memory-management techniques, including paging and segmentation To provide a detailed description of the Intel Pentium, which supports both pure segmentation and segmentation with paging Operating System Concepts – 9 th Edition 8. 2 Silberschatz, Galvin and Gagne © 2013

Background Program must be brought (from disk) into memory and placed within a process for it to be run Main memory and registers are only storage CPU can access directly Memory unit only sees a stream of addresses + read requests, or address + data and write requests Register access in one CPU clock (or less) But Main memory can take many cycles, causing a stall Cache sits between main memory and CPU registers Protection of memory required to ensure correct operation Operating System Concepts – 9 th Edition 8. 3 Silberschatz, Galvin and Gagne © 2013

Base and Limit Registers A pair of base and limit registers define the logical address space CPU must check every memory access generated in user mode to be sure it is between base and limit for that user Operating System Concepts – 9 th Edition 8. 4 Silberschatz, Galvin and Gagne © 2013

Address representation Address are represented in different ways during different steps Source program: addresses are symbolic like variables Compiler: binds symbolic addresses to relocatable Ex: 14 bytes from the beginning of this module Loader: binds relocatable addresses to absolute, Ex. 74014 Operating System Concepts – 9 th Edition 8. 6 Silberschatz, Galvin and Gagne © 2013

Binding of Instructions and Data to Memory Address binding of instructions and data to memory addresses can happen at different steps Compile time: if at some later time the starting location changes, then recompiling is necessary Load time: binding relocatable addresses (from compile time) to absolute addresses Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another Need hardware support for address maps (e. g. , base and limit registers) Operating System Concepts – 9 th Edition 8. 7 Silberschatz, Galvin and Gagne © 2013

Logical vs. Physical Address Space Logical address – generated by the CPU; also referred to as virtual address Physical address – address seen by the memory unit Logical address space is the set of all logical addresses generated by a program Physical address space is the set of all physical addresses corresponding to the program logical addresses Operating System Concepts – 9 th Edition 8. 8 Silberschatz, Galvin and Gagne © 2013

Memory-Management Unit (MMU) Hardware device that at run time maps virtual to physical address Usually a part of CPU The value in the relocation register is added to every address generated by a user process at the time it is sent to memory Base register now called relocation register The user program deals with logical addresses; it never sees the real physical addresses Operating System Concepts – 9 th Edition 8. 9 Silberschatz, Galvin and Gagne © 2013

Dynamic relocation using a relocation register Dynamic relocation and Logical addresses benefits: Routine is not loaded until it is called Better memory-space utilization; unused routine is never loaded All routines kept on disk in relocatable load format Simplify swapping; The swapped out process does not need to swap back in to same physical addresses Operating System Concepts – 9 th Edition 8. 10 Silberschatz, Galvin and Gagne © 2013

Memory allocation for process Fixed size Variable size Contiguous Allocation Causes p 0 Fixed size partitions internal fragmentation p 1 Variable size partitions Causes p 2 Variable size segments p 3 P 4 p 3 Paging p 1 p 2 external fragmentation Segmentation p 0 Fixed size pages Operating System Concepts – 9 th Edition 8. 12 Silberschatz, Galvin and Gagne © 2013

Fragmentation External Fragmentation – total memory space exists to satisfy a request, but it is not contiguous Internal Fragmentation – allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used Operating System Concepts – 9 th Edition 8. 13 Silberschatz, Galvin and Gagne © 2013

Solution to Fragmentation problem Reduce external fragmentation by compaction Shuffle memory contents to place all free memory together in one large block Compaction is possible only if relocation is dynamic, and is done at execution time Operating System Concepts – 9 th Edition 8. 14 Silberschatz, Galvin and Gagne © 2013

Segmentation Memory-management scheme that supports user view of memory A program is a collection of segments A segment is a logical unit such as: main program procedure function method object local variables, global variables common block stack symbol table arrays Operating System Concepts – 9 th Edition 8. 15 Silberschatz, Galvin and Gagne © 2013

Segmentation Architecture Logical address consists of a two tuple: <segment-number, offset>, Segment table – maps two-dimensional physical addresses; each table entry has: base – contains the starting physical address where the segments reside in memory limit – specifies the length of the segment Segment-table base register (STBR) points to the segment table’s location in memory Segment-table length register (STLR) indicates number of segments used by a program; segment number s is legal if s < STLR Operating System Concepts – 9 th Edition 8. 18 Silberschatz, Galvin and Gagne © 2013

Segmentation: Example What is the physical addresses of below logical addresses according to the segment table? 2, 700 0, 150 Base Length 500 2, 700: Invalid 700 1000 0, 150: 500+150=650 1800 600 Operating System Concepts – 9 th Edition 8. 19 Silberschatz, Galvin and Gagne © 2013

Paging Divide physical memory into fixed-sized blocks called frames Size is power of 2, between 512 bytes and 16 Mbytes Divide logical memory into blocks of same size called pages Keep track of all free frames To run a program of size N pages, need to find N free frames and load program Set up a page table to translate logical to physical addresses Still have Internal fragmentation Operating System Concepts – 9 th Edition 8. 20 Silberschatz, Galvin and Gagne © 2013

Address Translation Scheme Address generated by CPU is divided into: Page number (p) – used as an index into a page table which contains base address of each page in physical memory Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit For given logical address space 2 m and page size 2 n Operating System Concepts – 9 th Edition 8. 21 Silberschatz, Galvin and Gagne © 2013

Paging: Example If the page size is equal to 1 KB, in logical address 000001011110, how many bits are required for the page number? 1 KB = 10 bits for page offset 000001011110 16 -10=6 bits for the page # 16 bits Operating System Concepts – 9 th Edition 8. 25 Silberschatz, Galvin and Gagne © 2013

Paging: Example There are 4 pages in a logical address space and each page has 2 words. If these pages are assigned to a physical address space with 8 frames, how many bits are required for physical and logical addresses? Logical address: 4 pages = 2 bits, 2 words=1 bit => 3 bits Physical address: 8 frames=3 bits, 2 words=1 bit => 4 bit Operating System Concepts – 9 th Edition 8. 26 Silberschatz, Galvin and Gagne © 2013

Paging (Cont. ) Calculating internal fragmentation Page size = 2, 048 bytes Process size = 72, 766 bytes 35 pages + 1, 086 bytes Internal fragmentation of 2, 048 - 1, 086 = 962 bytes Worst case fragmentation = 1 frame – 1 byte On average fragmentation = 1 / 2 frame size So small frame sizes desirable? But each page table entry takes memory to track Page sizes growing over time Solaris supports two page sizes – 8 KB and 4 MB Process view and physical memory now very different By implementation process can only access its own memory Operating System Concepts – 9 th Edition 8. 27 Silberschatz, Galvin and Gagne © 2013

Implementation of Page Table Page table is kept in main memory Page-table base register (PTBR) points to the page table Page-table length register (PTLR) indicates size of the page table In this scheme every data/instruction access requires two memory accesses One for the page table and one for the data / instruction The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation lookaside buffers (TLBs) Operating System Concepts – 9 th Edition 8. 28 Silberschatz, Galvin and Gagne © 2013

Increasing or Decreasing page size What is the benefits of increasing page size? In what situation do you suggest to increase the page size? Operating System Concepts – 9 th Edition 8. 29 Silberschatz, Galvin and Gagne © 2013

Paging and segmentation Combination What if paging and segmentation used simultaneously? What is the fields of a logical address? How the physical address is achieved from a logical address? What are the benefits? Operating System Concepts – 9 th Edition 8. 30 Silberschatz, Galvin and Gagne © 2013