CHAPTER 7 The CPU and Memory The Architecture

CHAPTER 7: The CPU and Memory § The Architecture of Computer Hardware and Systems Software: An Information Technology Approach § 3 rd Edition, Irv Englander § John Wiley and Sons 2003

CPU: 3 Major Components § ALU (arithmetic logic unit) § Performs calculations and comparisons (data changed) § CU (control unit): performs fetch/execute cycle § Functions: p p Moves data to and from CPU registers and other hardware components (no change in data) Accesses program instructions and issues commands to the ALU § Subparts: p p Memory management unit: supervises fetching instructions and data I/O Interface: sometimes combined with memory management unit as Bust Interface Unit § Registers § Example: Program counter (PC) or instruction pointer determines next instruction for execution Chapter 7 CPU and Memory 2

System Block Diagram Chapter 7 CPU and Memory 3

The Little Man Computer Chapter 7 CPU and Memory 4

Concept of Registers § Small, permanent storage locations within the CPU used for a particular purpose § Manipulated directly by the Control Unit § Wired for specific function § Size in bits or bytes (not MB like memory) § Can hold data, an address or an instruction § How many registers does the LMC have? Chapter 7 CPU and Memory 5

Registers § Use of Registers § Scratchpad for currently executing program p Holds data needed quickly or frequently § Stores information about status of CPU and currently executing program p p Address of next program instruction Signals from external devices § General Purpose Registers § § User-visible registers Hold intermediate results or data values, e. g. , loop counters Equivalent to LMC’s calculator Typically several dozen in current CPUs Chapter 7 CPU and Memory 6

Special-Purpose Registers § Program Count Register (PC) § Also called instruction pointer § Instruction Register (IR) § Stores instruction fetched from memory § Memory Address Register (MAR) § Memory Data Register (MDR) § Status Registers § Status of CPU and currently executing program § Flags (one bit Boolean variable) to track condition like arithmetic carry and overflow, power failure, internal computer error Chapter 7 CPU and Memory 7

Register Operations § Stores values from other locations (registers and memory) § Addition and subtraction § Shift or rotate data § Test contents for conditions such as zero or positive Chapter 7 CPU and Memory 8

Operation of Memory § Each memory location has a unique address § Address from an instruction is copied to the MAR which finds the location in memory § CPU determines if it is a store or retrieval § Transfer takes place between the MDR and memory § MDR is a two way register Chapter 7 CPU and Memory 9

Relationship between MAR, MDR and Memory Address Chapter 7 CPU and Memory Data 10

MAR-MDR Example Chapter 7 CPU and Memory 11

Visual Analogy of Memory Chapter 7 CPU and Memory 12

Individual Memory Cell Chapter 7 CPU and Memory 13

Memory Capacity § Determined by two factors 1. Number of bits in the MAR p p LMC = 100 (00 to 99) 2 K where K = width of the register in bits 2. Size of the address portion of the instruction p p p 4 bits allows 16 locations 8 bits allows 256 locations 32 bits allows 4, 294, 967, 296 or 4 GB § Important for performance § Insufficient memory can cause a processor to work at 50% below performance Chapter 7 CPU and Memory 14

RAM: Random Access Memory § DRAM (Dynamic RAM) § Most common, cheap § Volatile: must be refreshed (recharged with power) 1000’s of times each second § SRAM (static RAM) § Faster than DRAM and more expensive than DRAM § Volatile § Frequently small amount used in cache memory for high-speed access used Chapter 7 CPU and Memory 15

ROM - Read Only Memory § Non-volatile memory to hold software that is not expected to change over the life of the system § Magnetic core memory § EEPROM § Electrically Erasable Programmable ROM § Slower and less flexible than Flash ROM § Faster than disks but more expensive § Uses p p BIOS: initial boot instructions and diagnostics Digital cameras Chapter 7 CPU and Memory 16

Fetch-Execute Cycle § Two-cycle process because both instructions and data are in memory § Fetch § Decode or find instruction, load from memory into register and signal ALU § Execute § Performs operation that instruction requires § Move/transform data Chapter 7 CPU and Memory 17

LMC vs. CPU Fetch and Execute Cycle Chapter 7 CPU and Memory 18

Load Fetch/Execute Cycle 1. PC -> MAR Transfer the address from the PC to the MAR 2. MDR -> IR Transfer the instruction to the IR 3. IR(address) -> MAR 4. MDR -> A Address portion of the instruction loaded in MAR Actual data copied into the accumulator 5. PC + 1 -> PC Program Counter incremented Chapter 7 CPU and Memory 19

Store Fetch/Execute Cycle 1. PC -> MAR 2. MDR -> IR 3. IR(address) -> MAR 4. A -> MDR* 5. PC + 1 -> PC Transfer the address from the PC to the MAR Transfer the instruction to the IR Address portion of the instruction loaded in MAR Accumulator copies data into MDR Program Counter incremented *Notice how Step #4 differs for LOAD and STORE Chapter 7 CPU and Memory 20

ADD Fetch/Execute Cycle 1. PC -> MAR Transfer the address from the PC to the MAR 2. MDR -> IR Transfer the instruction to the IR 3. IR(address) -> MAR 4. A + MDR -> A Address portion of the instruction loaded in MAR Contents of MDR added to contents of accumulator 5. PC + 1 -> PC Program Counter incremented Chapter 7 CPU and Memory 21

LMC Fetch/Execute SUBTRACT IN OUT HALT PC MAR MDR IR IR[addr] MAR IOR A A IOR A – MDR A PC + 1 PC BRANCH on Condition PC MAR MDR IR IR[addr] PC If condition false: PC + 1 PC If condition true: IR[addr] PC Chapter 7 CPU and Memory 22

Bus § The physical connection that makes it possible to transfer data from one location in the computer system to another § Group of electrical conductors for carrying signals from one location to another § Line: each conductor in the bus § 4 kinds of signals 1. Data (alphanumeric, numerical, instructions) 2. Addresses 3. Control signals 4. Power (sometimes) Chapter 7 CPU and Memory 23

Bus § Connect CPU and Memory § I/O peripherals: on same bus as CPU/memory or separate bus § Physical packaging commonly called backplane § Also called system bus or external bus § Example of broadcast bus § Part of printed circuit board called motherboard that holds CPU and related components Chapter 7 CPU and Memory 24

Bus Characteristics § Protocol § Documented agreement for communication § Specification that spells out the meaning of each line and each signal on each line § Throughput, i. e. , data transfer rate in bits per second § Data width in bits carried simultaneously Chapter 7 CPU and Memory 25

Point-to-point vs. Multipoint Plug-in device Chapter 7 CPU and Memory Broadcast bus Example: Ethernet Shared among multiple devices 26

Motherboard § Printed circuit board that holds CPU and related components including backplane Chapter 7 CPU and Memory 27

Typical PC Interconnections Bus interface bridges connect different bus types Chapter 7 CPU and Memory 28

PCI Bus Connections Chapter 7 CPU and Memory 29

Instructions § Instruction § Direction given to a computer § Causes electrical signals to be sent through specific circuits for processing § Instruction set § Design defines functions performed by the processor § Differentiates computer architecture by the p p p Number of instructions Complexity of operations performed by individual instructions Data types supported Format (layout, fixed vs. variable length) Use of registers Addressing (size, modes) Chapter 7 CPU and Memory 30

Instruction Elements § OPCODE: task § Source OPERAND(s) § Result OPERAND Addresses § Location of data (register, memory) Explicit: included in instruction p Implicit: default assumed p OPCODE Chapter 7 CPU and Memory Source OPERAND Result OPERAND 31

Instruction Format § Machine-specific template that specifies § Length of the op code § Number of operands § Length of operands Simple 32 -bit Instruction Format Chapter 7 CPU and Memory 32

Instruction Formats: CISC Chapter 7 CPU and Memory 33

Instruction Formats: RISC Chapter 7 CPU and Memory 34

Instruction Types § Data Transfer (load, store) § Most common, greatest flexibility § Involve memory and registers § What’s a word ? 16? 32? 64 bits? § Arithmetic § Operators + - / * ^ § Integers and floating point § Logical or Boolean § Relational operators: > < = § Boolean operators AND, OR, XOR, NOR, and NOT § Single operand manipulation instructions § Negating, decrementing, incrementing Chapter 7 CPU and Memory 35

More Instruction Types § Bit manipulation instructions § Flags to test for conditions § § § Shift and rotate Program control Stack instructions Multiple data instructions I/O and machine control Chapter 7 CPU and Memory 36

Register Shifts and Rotates Chapter 7 CPU and Memory 37

Program Control Instructions § Program control § Jump and branch § Subroutine call and return Chapter 7 CPU and Memory 38

Stack Instructions § Stack instructions § LIFO method for organizing information § Items removed in the reverse order from that in which they are added Push Chapter 7 CPU and Memory Pop 39

Fixed Location Subroutine Return Address Storage: Oops! Chapter 7 CPU and Memory 40

Stack Subroutine Return Address Storage Chapter 7 CPU and Memory 41

Multiple Data Instructions § Perform a single operation on multiple pieces of data simultaneously § SIMD: Single Instruction, Multiple Data § Intel MMX : 57 multimedia instruction § Commonly used in vector and array processing applications Chapter 7 CPU and Memory 42