Chapter 7 Parallel Ports Basic Concepts of IO

Chapter 7 Parallel Ports

Basic Concepts of I/O • I/O devices are also called peripheral devices. • I/O devices are pieces of equipment that exchange data with a computer. – Examples include switches, light-emitting diodes, cathode-ray tube screens, printers, modems, keyboards, and disk drives.

Interface (Peripheral) Chip (1 of 2) • A chip whose function is to synchronize data transfer between the CPU and I/O devices • Consists of control registers, status registers, data direction latches, and control circuitry • Has pins that are connected to the CPU and I/O port pins that are connected to the I/O devices • Each interface chip has a chip enable signal input or inputs, when asserted, allow the interface chip to react to the data transfer request. • Data transfer between an I/O device and the CPU can be proceeded bit-by-bit or in multiple bits (parallel).

Interface (Peripheral) Chip (2 of 2) • Address decoder makes sure that each time one and only one peripheral device responds to the CPU’s I/O request.

I/O Schemes • Isolated I/O scheme – The microprocessor has dedicated instructions for I/O operations. – The microprocessor has a separate address space for I/O devices. • Memory-mapped I/O scheme – The microprocessor uses the same instruction set to perform memory accesses and I/O operations. – The I/O devices and memory components are resident in the same memory space.

I/O Transfer Synchronization • The role of an interface chip – Synchronizing data transfer between the CPU and the interface chip – Synchronizing data transfer between the interface chip and the I/O device

Synchronizing the Microprocessor and the Interface Chip • The polling method – For input -- The microprocessor checks a status bit of the interface chip to find out if the interface chip has received new data from the input device. – For output -- The microprocessor checks a status bit of the interface chip to find out if it can send new data to the interface chip. • The interrupt-driven method – For input -- The interface chip interrupts the microprocessor whenever it has received new data from the input device. – For output -- The interface chip interrupts the microprocessor whenever it can accept new data from the microprocessor.

Synchronizing the Interface Chip and the I/O Devices • Brute-force method -- useful when the data timing is unimportant – For input -- Nothing special is done. The microprocessor reads the interface chip and the interface chip returns the voltage levels on the input port pins to the microprocessor. – For output -- Nothing special is done. The interface chip places the data that it received from the microprocessor directly on the output port pins. • The strobe method -- a strobe signal used to indicate that data are stable on I/O port pins – For input -- The interface chip latches the data into its data register using the strobe signal. – For output -- The interface chip places the data on port pins that it received from the microprocessor and asserts the strobe signal. The output device latches the data using the strobe signal. • The handshake method -- used when timing is crucial – Two handshake signals used to synchronize the data transfer. One signal, call it H 1, is asserted by the interface chip. The other signal, call it H 2, is asserted by the I/O device. – Two handshake modes available • Pulse mode and interlocked mode

Input Handshake Protocol • Step 1. The interface chip asserts (or pulses) H 1 to indicate its intention to input data. • Step 2. The input device puts data on the data port pins and also asserts (or pulses) the handshake signal H 2. • Step 3. The interface chip latches the data and de-asserts H 1. After some delay, the input device also de-asserts H 2.

Output Handshake Protocol • Step 1. The interface chip places data on the port pins and asserts (or pulses) H 1 to indicate that it has valid data to be output. • Step 2. The output device latches the data and asserts (or pulses) H 2 to acknowledge the receipt of data. • Step 3. The interface chip deasserts H 1 following the assertion of H 2. The output device then de-asserts H 2.

Overview of HCS 12 Parallel Ports (1 of 3) • The HCS 12 members have from 48 to 144 I/O pins arranged in 3 to 12 ports and packaged in a quad flat pack (QFP) or low profile quad flat pack (LQFP). • All I/O pins serve multiple functions. • When a peripheral function is enabled, its associated pins cannot be used as I/O pins. • Each I/O port has several registers to support its operation. • Registers related to I/O ports have been assigned a mnemonic name and the user can use these names to refer to them: movb #$FF, PTA ; output $FF to Port A

Overview of HCS 12 Parallel Ports (2 of 3) • All I/O ports (except PAD 0 and PAD 1) have an associated data direction register and a data register. • The name of the data direction register is formed by adding the letters “DDR” as the prefix to the port name. For example, DDRA, DDRB, and DDRT. • To configure a pin for output, write a ‘ 1’ to the associated bit in the data direction register. • To configure a pin for input, write a ‘ 0’ to the associated bit in the data direction register. movb #$FF, DDRA movb #0, DDRA bset DDRA, $81 ; configure port A for output ; configure port A for input ; configure Port A pin 7 and 1 for output

Overview of HCS 12 Parallel Ports (3 of 3) • The name of port data register is formed by adding letters “PT” as the prefix to the port name. For example, PTA, PTB, PTP, and PTT. • We can also use “PORT” as the prefix to the port name for port A, B, E, and K. • Output a value to a port is done by storing that value to the port data register. movb #$FF, DDRH #$37, PTH ; configure Port H for output ; output the hex value 37 to port H • Input a value from an input port is done by loading from the port data register. movb ldaa #0, DDRH ; configure Port H for input PTH ; read data from port H into A • An I/O port may have up to eight associated registers.

Port A and Port B • In expanded mode, Port A carries the timemultiplexed higher address/data signals A 15/D 15…A 8/D 8. • In expanded mode, Port B carries the timemultiplexed lower address/data signals A 7/D 7…A 0/D 0. • In single chip mode, these two ports are used as general I/O ports.

Port E • Port E pins are used for bus control and interrupt service request signals. • When a Port E pin is not used as control or interrupt signal, it can be used as general I/O pin.

Port E Registers • Port E assignment register (PEAR) – In expanded mode, the PEAR register assigns the function of each port E pin. • MODE register – This register establishes the operation mode and other miscellaneous functions. • Pull-up control register (PUCR) – This register selects the pull-up resistors for the pins associated with the core ports. – Port A, B, E, and K are in the core part. • Reduced drive register (RDRIV) – This register selects reduced drive for the pins associated with the core ports. – This gives reduced power consumption and reduced RFI with a slight increase in transition time. • External bus interface control register (EBICTL) – Only bit 0 is implemented (ESTR). – The ESTR bit enables/disables the E clock stretching.

Port K • Has PTK and DDRK registers • Carries expanded address XADDR 14…XADDR 19 in expanded mode • On the rising edge of the RESET signal, the value of the PK 7 pin is latched into the ROMON bit of the MISC register in expanded mode. If it is 1, the on-chip flash memory is enabled. – ROMON is forced to 1 in single chip mode.

Port T • Has Port T data register (PTT), Port T data direction register (DDRT), Port input register (PTIT), reduced drive register (RDRT), pull device enable register (PERT), and port polarity select register (PPST) – The PTIT register allows the user to read back the status of Port T pins. – The RDRT register can configure the drive strength (current output) of each port pin as either full or reduced load. – The PERT register is used to enable an input Port T pin pull-up or pull-down device. – The PPST register selects whether a pulldown or pull-down device is connected to the pin. • Port T pins are also used as timer input capture/output compare pin.

Port S • Port S pins are used as general I/O, serial communication interface, and serial peripheral interface pins. • Port S has a Port S wired-or mode register (WOMS) in addition to all registers associated with Port T.

Port M • Port M has all the equivalent registers that Port S has and also a module routing register (MODRR). – The MODRR configures the rerouting of CAN 0, CAN 4, SPI 0, SPI 1, and SPI 2 on defined port pins.

• Example 7. 1 Give an instruction to configure the MODRR register to achieve the following port routing: 1. CAN 0: use pins PM 1 and PM 0 2. CAN 1: use pins PM 3 and PM 2 3. CAN 2: use pins PM 5 and PM 4 4. CAN 3: use pins PM 7 and PM 6 5. I 2 C: use PJ 7 and PJ 6 6. SPI 0: use pins PS 7~PS 4 7. SPI 1: use pins PH 3~PH 0 8. SPI 2: use pins PH 7~PH 4 • Solution: This routing requirement can be achieved by preventing CAN 4 from using any port pins and keep the default routing after reset. -The following instruction will satisfy the requirement: movb #$60, MODRR ; CAN 4 must be disabled

• Example 7. 2 Give an instruction to configure the MODRR register to achieve the following port routing: 1. CAN 0: use pins PM 1 and PM 0 2. CAN 1: use pins PM 3 and PM 2 3. CAN 2: disabled 4. CAN 3: disabled 5. I 2 C: use PJ 7 and PJ 6 6. SPI 0: use pins PS 7~PS 4 7. SPI 1: use pins PP 3~PP 0 8. SPI 2: use pins PH 7~PH 4 • Solution: This routing requirement can be satisfied by the following instruction: movb #$40, MODRR ; CAN 2~CAN 4 must be disabled

Port H, J, and P • These three I/O ports have the same set of registers: – – – – • • Port I/O register (PTH, PTJ, PTP) Port Input Register (PTIH, PTIJ, PTIP) Port Data Direction Register (DDRH, DDRJ, DDRP) Port Reduced Drive Register (RDRH, RDRJ, RDRP) Port Pull Device Enable Register (PERH, PERJ, PERP) Port Polarity Select Register (PPSH, PPSJ, PPSP) Port Interrupt Enable Register (PIEH, PIEJ, PIEP) Port Interrupt Flag Register (PIFH, PIFJ, PIFP) These ports have edge-triggered interrupt capability in the wired-OR fashion. The SPI function pins can be rerouted to Port H and P. The interrupt edges can be rising or falling and are programmed through Port Device Enable Register and Port Polarity Select Register. The Port Interrupt Register allows the user to enable interrupts on these three ports.

Port AD 0 and AD 1 • Many HCS 12 devices have two 8 -channel A/D converters (AD 0 and AD 1). • Device that has only one 8 -channel module is referred to as AD. • When A/D functions are disabled, these two ports can be used as general input port. • These two ports do not have data direction registers. • Each module has a Digital Input Enable Register. In order to use an A/D pin as a digital input, one needs to set its associated bit in this register.

Electrical Characteristic Consideration for I/O Interfacing • When interfacing I/O device to the MCU, one needs to consider electrical compatibility issues. – There are two electrical compatibility issues: • Voltage level compatibility • Current drive capability • There are many IC technologies in use. Some are bipolar, whereas others are unipolar (mainly CMOS and BICMOS). • Voltage parameters related to electrical compatibility – – Input high voltage (VIH) Input low voltage (VIL) Output high voltage (VOH) Output low voltage (VOL)

For Device X to Drive Device Y Correctly • The output high voltage of device X (VOHX) must be higher than the input high voltage of device Y (VIHY). • The output low voltage of device X (VOLX) must be lower than the input low voltage of device Y (VILY). • The input and output voltage levels of several popular logic families are shown in Table 7. 3. • At the same power supply level, the CMOS device has no problem in driving the bipolar and CMOS devices. • Bipolar devices have problem in driving CMOS devices. • HCS 12 cannot be driven by bipolar devices. • Bipolar devices have problems driving CMOS devices (including HCS 12).

Current Drive Capability • The device that drives other devices must have enough sourcing (supply current) and sinking (absorb current) capability. • Current flows out from the driving device when the driving voltage is high. • Current flows into the driving device when the driving voltage is low. • The driving device must be able to supply (or sink) enough current needed by those devices being driven for properation. • If a device cannot source or sink enough current, then using buffer device is a common solution. • The current capabilities of a logic device are determined by the following currents: – – Input high current (IIH) Input low current (IIL) Output high current (IOH) Output low current (IOL) • The current capability of several logic chip families are shown in Table 7. 4.

1. The IOH of an output pin must be equal to or larger than the total current flowing into all the peripheral pins that are connected to this pin. 2. The IOL of an output pin must be equal to or larger than the total current flowing out from all the peripheral pins that are connected to this pin.

Timing Compatibility • There is no timing problem when driving a peripheral pin that does not contain latches or flip-flops. • When driving a latch or flip-flop device, one needs to make sure that the data set up time (t. SU) and data hold time (t. HD) are both satisfied. • The data setup time and data hold time requirements are illustrated in Figure 7. 28.

Interfacing with LED Devices • Figure 7. 29 suggests three methods for interfacing with LEDs. • Circuit (a) and (b) are recommended for LEDs that need only small current to light. • Circuit (c) is recommended for LEDs that need larger current to light.

• Example 7. 3 Use Port B to drive eight LEDs using the circuit shown in Figure 7. 30. Light each LED for half a second in turn and repeat assuming the HCS 12 has a 24 -MHz E clock. - To turn on one LED at a time for half a second in turn, one should output the value $80, $40, $20, $10, $08, $04, $02, and $01 and stay for half a second in each value.

The assembly program that performs the operation is as follows: forever led_lp led_tab #include "C: miniidehcs 12. inc" org $1500 movb #$FF, DDRB ; configure port B for output bset DDRJ, $02 ; configure PJ 1 pin for output bclr PTJ, $02 ; enable LEDs to light ldaa #16 ; initialize loop count to 8 ldx #led_tab ; use X as the pointer to LED pattern table movb 1, x+, PTB ; turn on one LED ldy #5 ; wait for half a second jsr delayby 100 ms ; " dbne a, led_lp ; reach the end of the table yet? bra forever ; start from beginning dc. b $80, $40, $20, $10, $08, $04, $02, $01 dc. b $01, $02, $04, $08, $10, $20, $40, $80 #include "C: miniidedelay. asm" end

The C language version of the program is as follows: #include "c: egnu 091includehcs 12. h" #include "c: egnu 091includedelay. c" main (void) { char led_tab[8] = {0 x 80, 0 x 40, 0 x 20, 0 x 10, 0 x 08, 0 x 04, 0 x 02, 0 x 01, 0 x 02, 0 x 04, 0 x 08, 0 x 10, 0 x 20, 0 x 40, 0 x 80}; char i; DDRB = 0 x. FF; /* configure port B for output */ DDRJ |= 0 x 02; /* configure PJ 1 pin for output (needed for DRAGON 12 board only) */ PTJ &= 0 x. FD; /* enable LEDs to light (needed for DRAGON 12 board only)*/ while (1){ for (i = 0; i < 16; i++) { PTB = led_tab[i]; delayby 100 ms(5); } } return 0; }

Driving a Single Seven-Segment Display • A common cathode seven-segment display is driven by the 74 HC 244 via resistors. • The output high voltage of the 74 HC 244 is close to 5 V with a 5 V power supply. • The segment patterns for 0 to 9 are shown in Table 7. 5.

Driving Multiple Seven-Segment Displays • Time multiplexing technique is often used to drive multiple displays in order to save I/O pins. • One parallel port is used to drive the segment pattern and the other port turns on one display at a time. Each display is turned on and then off many times within a second. The persistence of vision make us feel that all displays are turned on simultaneously.

• Example 7. 4 Write a sequence of instructions to display 4 on the seven-segment display #4 in Figure 7. 32. • Solution: To display the digit 4 on the display #4, we need to: – Output the hex value $33 to port B – Set the PK 4 pin to 1 – Clear pins PK 5 and PK 3. . . P 0 to 0 four #include <hcs 12. inc> equ $33 movb #$3 F, DDRK movb #$FF, DDRB bset PTK, $10 bclr PTK, $2 F movb #four, PTB In C language: DDRK DDRB PTK PTB = 0 x 3 F; = 0 x. FF; = 0 x 10; = 0 x 33; ; seven-segment pattern of digit 4 ; configure PORT K for output ; configure PORT B for output ; turn on seven-segment display #4 ; turn off seven-segment displays #5, #3…#0 ; output the seven-segment pattern to PORTP

• Example 7. 5 Write a program to display 123456 on the six seven-segment displays shown in Figure 7. 32. • Solution: Display 123456 on display #5, #4, #3, #2, #1, and #0, respectively. • The values to be output to Port B and Port K to display one digit at a time is shown in Table 7. 6. - The program logic is shown in Figure 7. 33.

#include pat_port equ pat_dir equ sel_port equ sel_dir equ org movb forever ldx loop movb ldy jsr cpx bne bra #include disp_tab dc. b end "c: miniidehcs 12. inc" PTB ; Port that drives the segment pattern DDRB ; direction register of the segment pattern PTK ; Port that selects the digit DDRK ; data direction register of the digit select port $1500 #$FF, pat_dir ; configure pattern port for output #$3 F, sel_dir ; configure digit select port for output #disp_tab ; use X as the pointer 1, x+, pat_port ; output digit pattern and move the pointer 1, x+, sel_port ; output digit select value and move the pointer #1 ; wait for 1 ms delayby 1 ms ; “ #disp_tab+12 ; reach the end of the table loop forever "c: miniidedelay. asm" $30, $20 ; seven-segment display table $6 D, $10 $79, $08 $33, $04 $5 B, $02 $5 F, $01

#include “c: egnu 091includehcs 12. h” #include “c: egnu 091includedelay. c” #define pat_port PTB /* segment pattern port */ #define pat_dir DDRB /* pattern port data direction register */ #define sel_port PTK /* digit select port */ #define sel_dir DDRK /* digit select port direction register */ main (void) { char disp_tab[6][2] = {{0 x 30, 0 x 20}, {0 x 6 D, 0 x 10}, {0 x 79, 0 x 08}, {0 x 33, 0 x 04}, {0 x 5 B, 0 x 02}, {0 x 5 F, 0 x 01}}; char i; pat_dir = 0 x. FF; /* configure pat_port for output */ sel_dir = 0 x 3 F; /* configure sel_port for output */ while (1) { for (i = 0; i < 6; i++) { pat_port = disp_tab[i][0]; /* output the segment pattern */ sel_port = disp_tab[i][1]; /* turn on the display */ delaybyms(1); /* wait for 1 ms */ } } return 0; }

Liquid Crystal Display (LCD) (1 of 2) • The basic construction of an LCD is illustrated in Figure 7. 34. • The most common type of LCD allows the light to pass through when activated. • An LCD segment is activated when a low frequency bipolar signal in the range of 30 Hz to 1 KHz is applied to it. • LCD can display characters and graphics. • LCDs are often sold in a module with LCDs and controller unit built in. • The Hitachi HD 44780 is the most popular LCD controller being used today.

Liquid Crystal Display (LCD) (2 of 2)

A HD 44780 -Based LCD Kit (1 of 3) • • Display capability: 4 x 20 Uses the HD 44780 as the controller as shown in Figure 7. 35. Pins DB 7~DB 0 are used to exchange data with the CPU. E input should be connected to one of the address decoder output or I/O pin. The RS signal selects instruction register (0) or data register (1). The VEE signal allows the user to adjust the LCD contrast. The HD 44780 can be configured to display 1 -line, 2 -line, and 4 -line information. The pin assignment for character-based LCD module with less than and more than 80 characters are shown in Table 7. 7 and 7. 8.

A HD 44780 -Based LCD Kit (2 of 3)

A HD 44780 -Based LCD Kit (3 of 3)

HD 44780 Commands (1 of 4)

HD 44780 Commands (2 of 4)

HD 44780 Commands (3 of 4) • The HD 44780 has a display data RAM (DDRAM) to store data to be displayed on the LCD. • The address range of DDRAM for 1 -line, 2 -line, and 4 -line LCDs are shown in Table 7. 11 a, 7. 11 b, and 7. 11 c. • The HD 44780 has a character generator ROM that can generates 5 8 or 5 10 character patterns from a 8 -bit code. • The user can rewrite character patterns into the character generator RAM (CGRAM). • Up to eight 5 8 patterns or four 5 10 patterns can be programmed.

HD 44780 Commands (4 of 4)

Registers of HD 44780 • • The HD 44780 has two 8 -bit user accessible registers: instruction register (IR) and data register (DR). To write data into display data RAM or character generator RAM, the MCU writes into the DR register. The address of the data RAM should be set up with a previous instruction. The DR register is also used for data storage when reading data from DDRAM or CGRAM. The register selection is shown in Table 7. 12. The HD 44780 has a busy flag that is output from the DB 7 pin. The HD 44780 uses a 7 -bit address counter to keep track of the address of the next DDRAM or CGRAM location to be accessed.

HD 44780 Instructions (1 of 3) • Clear display – Writes 0 x 20 (space character) to all DDRAM locations – Sets 0 to the address counter (return cursor to upper left corner of the LCD) – Sets increment mode • Return home – Sets address counter to 0 – DDRAM contents not changed • Entry mode set – Sets incrementing or decrementing of the DDRAM address – Controls the shifting (shifts if S bit = 1) of the display • Display on/off control – Turns on/off display – Turns on/off cursor blinking

HD 44780 Instructions (2 of 3) • Cursor or display shift – This function shifts the cursor position to the right or left without writing or reading display data. – The shifting is controlled by two bits as shown in Table 7. 13. • Function set – Sets the interface length (DL bit) to be 4 - or 8 -bit – Selects the number of lines (N bit) to be one or two lines – Selects character font (F bit) to be 5 8 or 5 10

HD 44780 Instructions (3 of 3) • Set CGRAM address – This command contains the address to be written into the address counter. • Set DDRAM address – This command allows the user to set the starting address to display information. • Read busy flag and address – This command reads the busy flag and the address counter. – User can use this command to determine the LCD controller is ready to accept another command. – User can use this command to control where to start displaying information.

Interfacing the HD 44780 with the HCS 12 • One can treat the LCD kit as an I/O device and use an I/O port and several other I/O pins as control signals. • The interface can be 4 bits or 8 bits. • To read or write the LCD successfully, one must satisfy the timing requirements of the LCD. The timing diagrams for read and write are shown in Figure 7. 37 and 7. 38.

• Procedure to send a command to the IR register – Step 1 • Pull the RS and the E signals to low. – Step 2 • Pull the R/W signal to low. – Step 3 • Pull the E signal to high. – Step 4 • Output data to the output port attached to the LCD data bus. One needs to configure the I/O Port for output before writing data to the LCD kit. – Step 5 • Pull the E signal to low and make sure that the internal operation is complete.

• The procedure for writing a byte to the LCD data register – Step 1 • Pull the RS signal to high. – Step 2 • Pull the R/W signal to low. – Step 3 • Pull the E signal to high. – Step 4 • Output data to the I/O port attached to the LCD data bus. – Step 5 • Pull the E signal to low and make sure that the internal operation is complete. • These procedures need to be repeated once for an LCD kit with 4 -bit interface.

• Write a function to send a command to the LCD kit – Most LCD commands are completed in 40 ms. – If the function waits for 40 ms after performing the specified operation, then most commands will be completed when the function returns. – The assembly code for the 8 -bit interface is as follows: lcd. Port equ PTH ; LCD data port lcd. Ctl equ PTK ; LCD control port lcd. E equ $80 ; E signal pin (PK 7) lcd. RW equ $20 ; R/W signal pin (PK 5) lcd. RS equ $10 ; RS signal pin (PK 4) ; the command is contained in A cmd 2 lcd bclr lcd. Ctl, lcd. RS+lcd. RW ; select instruction register and Write bset lcd. Ctl, lcd. E ; pull the E signal high staa lcd. Port ; send the command, along with RS, E signals nop bclr lcd. Ctl, lcd. E ; pull the E signal low bset lcd. Ctl, lcd. RW ; pull R/W to high ldy #1 ; adding this delay will complete the internal jsr delayby 50 us ; operation for most instructions rts

• The function to configure LCD sends four commands to the LCD kit – – Entry mode set Display on/off Function set Clear display lcd. DIR equ lcd. Ctl. DIR equ openlcd movb bset ldy jsr ldaa jsr ldy jsr rts DDRH DDRK #$FF, lcd. DIR lcd. Ctl. Dir, $B 0 #5 delayby 100 ms #$38 cmd 2 lcd #$0 F cmd 2 lcd #$06 cmd 2 lcd #$01 cmd 2 lcd #2 delayby 1 ms ; configure port H for output ; configure control pins for output ; wait for LCD to complete internal ; configuration ; set 8 -bit data, 2 -line display, 5 x 8 font ; " ; turn on display, cursor, and blinking ; " ; move cursor right (entry mode set instruction) ; " ; clear LCD screen and return to home position ; " ; wait until "clear display" command is complete ; "

• Function to output a character to the LCD – The character to be output is in accumulator A. putc 2 lcd bset lcd. Ctl, lcd. RS bclr lcd. Ctl, lcd. RW bset lcd. Ctl, lcd. E staa lcd. Port nop bclr lcd. Ctl, lcd. E bset lcd. Ctl, lcd. RW ldy #1 jsr delayby 50 us rts ; select LCD Data register ; enable write to LCD ; pull E to high ; send data to LCD ; provide enough length to E signal ; " ; pull the E signal low ; pull R/W high to complete the write cycle ; wait until the write operation is ; complete

• Function to output a string terminated by a NULL character – The string to be output is pointed to by index register X. puts 2 lcd ldaa beq jsr bra done_puts rts 1, x+ done_puts putc 2 lcd puts 2 lcd ; get one character from the string ; reach NULL character? • Example 7. 7 Write an assembly program to test the previous four subroutines by displaying the following messages on two lines: hello world! I am ready!

#include lcd. Port lcd. DIR lcd. Ctl. Dir lcd. E lcd. RW lcd. RS "hcs 12. inc" equ PTH ; LCD data pins (PH 7~PH 0) equ DDRH ; LCD data direction port equ PTK ; LCD control port equ DDRK ; LCD control port direction equ $80 ; E signal pin equ $20 ; R/W signal pin equ $10 ; RS signal pin org $1500 lds #$1500 ; set up stack pointer jsr openlcd ; initialize the LCD ldx #msg 1 lcd jsr puts 2 lcd ldaa #$C 0 ; move to the second row jsr cmd 2 lcd ; " ldx #msg 2 lcd jsr puts 2 lcd swi msg 1 lcd fcc "hello world!" dc. b 0 msg 2 lcd fcc "I am ready!" dc. b 0 #include “c: miniidedelay. asm" ; include delay routines here ; include the previous four LCD functions

#define #define void void { } lcd. Port PTH lcd. DIR DDRH lcd. E 0 x 80 lcd. RW 0 x 20 lcd. RS 0 x 10 lcd. Ctl. DIR DDRK cmd 2 lcd (char cmd); openlcd (void); putc 2 lcd (char cx); puts 2 lcd (char *ptr); cmd 2 lcd (char cmd) /* Port H drives LCD data pins */ /* Direction of LCD port */ /* E signal (PK 7) */ /* R/W signal (PK 5) */ /* RS signal (PK 4) */ /* LCD control port direction */ char temp; char xa, xb; lcd. Ctl &= ~(lcd. RS+lcd. RW); /* select instruction register & pull R/W low */ lcd. Ctl |= lcd. E; /* pull E signal to high */ lcd. Port = cmd ; /* output command */ xa = 1; /* dummy statements to lengthen E */ xb = 2; /* " */ lcd. Ctl &= ~lcd. E; /* pull E signal to low */ lcd. Ctl |= lcd. RW; /* pull R/W to high */ delayby 50 us(1); /* wait until the command is complete */

void openlcd(void) { lcd. DIR = 0 x. FF; lcd. Ctl. DIR = 0 x. B 0; delayby 100 ms(5); cmd 2 lcd (0 x 38); cmd 2 lcd (0 x 0 F); cmd 2 lcd (0 x 06); cmd 2 lcd (0 x 01); delayby 1 ms (2); } /* configure lcd. Port port for output */ /* configure LCD control pins for output */ /* wait for LCD to become ready */ /* set 8 -bit data, 2 -line display, 5 x 8 font */ /* turn on display, cursor, blinking */ /* move cursor right */ /* clear screen, move cursor to home */ /* wait until "clear display" command is complete */

void putc 2 lcd(char cx) { char temp; char xa, xb; lcd. Ctl |= lcd. RS; lcd. Ctl &= ~lcd. RW; lcd. Ctl |= lcd. E; lcd. Port = cx; xa = 1; xb = 2; lcd. Ctl &= ~lcd. E; lcd. Ctl |= lcd. RW; delayby 50 us(1); } void puts 2 lcd (char *ptr) { while (*ptr) { putc 2 lcd(*ptr); ptr++; } } /* select LCD data register and pull R/W high*/ /* pull R/W to low */ /* pull E signal to high */ /* output data byte */ /* create enough width for E */ /* pull E to low */ /* pull R/W signal to high */

• Write a C program to test the SSE 256 LCD functions. #include "c: egnu 091includehcs 12. h" #include "c: egnu 091includedelay. c" #include “c: egnu 091includelcd_util_SSE 256. c” main (void) { char *msg 1 = "hello world!"; char *msg 2 = "I am ready!"; openlcd(); cmd 2 lcd(0 x 80); /* move cursor to the 1 st column of row 1 */ puts 2 lcd(msg 1); cmd 2 lcd(0 x. C 0); /* move cursor to 2 nd row, 1 st column */ puts 2 lcd(msg 2); return 0; }

Interfacing with DIP Switches (1 of 2) • Switches are often grouped together. It is most common to have four or eight switches in a DIP package. • DIP switches are often used to provide setup information to the microcontroller. After power is turned on, the microcontroller reads the settings of the DIP switches and performs accordingly.

Interfacing with DIP Switches (2 of 2) • Example 7. 9 Write a sequence of instructions to read the value from an eight-switch DIP connected to PORTA of the HCS 12 into accumulator A. • Solution #include “c: miniidehcs 12. inc” movb #0, DDRA ; configure Port A for input ldaa PTA ; read Port A In C language: #include “c: egnu 091includehcs 12. h” void main () { char xx; DDRA = 0; xx = PTA; }

Interfacing to a Keyboard • A keyboard is arranged as an array of switches, which can be mechanical, membrane, capacitors, or Hall-effect in construction. • Mechanical switches are most popular for keyboards. – Mechanical switches have a problem called contact bounce. Closing a mechanical switch generates a series of pulses because the switch contacts do not come to rest immediately. – In addition, a human cannot type more than 50 keys in a second. Reading the keyboard more than 50 times a second will read the same key stroke too many times. • A keyboard input is divided into three steps: – Scan the keyboard to discover which key has been pressed. – Debounce the keyboard to determine if a key is indeed pressed. Both hardware and software approaches for key debouncing are available. – Lookup the ASCII table to find out the ASCII code of the pressed key.

Hardware Debouncing Techniques • SR latches • Non-inverting CMOS gates • Integrating debouncer

Software Debouncing Technique • The most popular and simple one has been the wait and see method. – In this method, the program simply waits for about 10 ms and reexamines the same key again to see if it is still pressed.

ASCII Code Table Lookup • The ASCII code of each key can be stored in a table for easy look up.

• • Interfacing the HCS 12 to a Keypad A keypad usually consists of 12 to 24 keys and is adequate for many applications. Like a keyboard, a keypad also needs debouncing. A 16 -key keypad can be easily interfaced to one of the HCS 12 parallel ports. A circuit that interfaces a 16 -key keypad is shown in Figure 7. 41. In this Figure, pins PA 7. . PA 4 each control four keys.

• Example 7. 10 Write a program to perform keypad scanning, debouncing, and returns the ASCII code in accumulator A to the caller. • Solution – Pins PA 4. . PA 7 each control one row of four keys. – Scanning is performed by setting one of the PA 7. . PA 4 pins to low, the other three pins to high and testing one key at a time. #include keyboard get_char scan_r 0 scan_k 1 scan_k 2 scan_k 3 key 0 key 1 “c: miniidehcs 12. inc" equ PTA movb brclr bra jmp #$F 0, DDRA #$EF, keyboard, $01, key 0 keyboard, $02, key 1 keyboard, $04, key 2 keyboard, $08, key 3 scan_r 1 db_key 0 db_key 1 ; set PA 7~PA 4 for output, PA 3~PA 0 for input ; scan the row containing keys 0123 ; is key 0 pressed? ; is key 1 pressed? ; is key 2 pressed? ; is key 3 pressed?

key 2 key 3 scan_r 1 scan_k 4 scan_k 5 scan_k 6 scan_k 7 key 4 key 5 key 6 key 7 scan_r 2 scan_k 8 scan_k 9 scan_k. A scan_k. B key 8 key 9 jmp movb brclr bra jmp jmp movb bclr brclr bra jmp db_key 2 db_key 3 #$DF, keyboard, $01, key 4 keyboard, $02, key 5 keyboard, $04, key 6 keyboard, $08, key 7 scan_r 2 db_key 4 db_key 5 db_key 6 db_key 7 #$BF, keyboard, $40 keyboard, $01, key 8 keyboard, $02, key 9 keyboard, $04, key. A keyboard, $08, key. B scan_r 3 db_key 8 db_key 9 ; scan the row containing keys 4567 ; is key 4 pressed? ; is key 5 pressed? ; is key 6 pressed? ; is key 7 pressed? ; scan the row containing keys 89 AB ; “ ; is key 8 pressed? ; is key 9 pressed? ; is key A pressed? ; is key B pressed?

key. A key. B scan_r 3 scan_k. C scan_k. D scan_k. E scan_k. F jmp movb brclr jmp key. C jmp key. D jmp key. E jmp key. F jmp ; debounce key 0 db_key 0 jsr brclr jmp getc 0 ldaa rts ; debounce key 1 db_key. A db_key. B #$7 F, keyboard, $01, key. C keyboard, $02, key. D keyboard, $04, key. E keyboard, $08, key. F scan_r 0 db_key. C db_key. D db_key. E db_key. F ; scan the row containing keys CDEF ; is key C pressed? ; is key D pressed? ; is key E pressed? ; is key F pressed? delay 10 ms keyboard, $01, getc 0 scan_k 1 #$30 ; return the ASCII code of 0

db_key 1 jsr brclr jmp getc 1 ldaa rts db_key 2 jsr brclr jmp getc 2 ldaa rts db_key 3 jsr brclr jmp getc 3 ldaa rts db_key 4 jsr brclr delay 10 ms keyboard, $02, getc 1 scan_k 2 #$31 ; return the ASCII code of 1 delay 10 ms keyboard, $04, getc 2 scan_k 3 #$32 ; return the ASCII code of 2 delay 10 ms keyboard, $08, getc 3 scan_r 1 #$33 ; return the ASCII code of 3 delay 10 ms keyboard, $01, getc 4

jmp getc 4 ldaa rts db_key 5 jsr brclr jmp getc 5 ldaa rts db_key 6 jsr brclr jmp getc 6 ldaa rts db_key 7 jsr brclr jmp scan_k 5 #$34 ; return the ASCII code of 4 delay 10 ms keyboard, $02, getc 5 scan_k 6 #$35 ; return the ASCII code of 5 delay 10 ms keyboard, $04, getc 6 scan_k 7 #$36 ; return the ASCII code of 6 delay 10 ms keyboard, $08, getc 7 scan_r 2

getc 7 db_key 8 getc 8 db_key 9 getc 9 db_key. A getc. A db_key. B getc. B ldaa rts jsr brclr jmp ldaa rts #$37 ; return the ASCII code of 7 delay 10 ms keyboard, $01, getc 8 scan_k 9 #$38 ; return the ASCII code of 8 delay 10 ms keyboard, $02, getc 9 scan_k. A #$39 ; return the ASCII code of 9 delay 10 ms keyboard, $04, getc. A scan_k. B #$41 ; get the ASCII code of A delay 10 ms keyboard, $08, getc. B scan_r 3 #$42 ; get the ASCII code of B

db_key. C getc. C db_key. D getc. D db_key. E getc. E db_key. F getc. F jsr brclr jmp ldaa rts delay 10 ms keyboard, $01, getc. C scan_k. D #$43 ; get the ASCII code of C jsr brclr jmp ldaa rts delay 10 ms keyboard, $04, getc. E scan_k. F #$45 ; get the ASCII code of E delay 10 ms keyboard, $02, getc. D scan_k. E #$44 ; get the ASCII code of D delay 10 ms keyboard, $08, getc. F scan_r 0 #$46 ; get the ASCII code of F

delay 10 ms movb ldd addd std wait_lp 2 brclr rts #$90, TSCR 1 #$06, TSCR 2 #$01, TIOS TCNT #3750 TC 0 TFLG 1, $01, wait_lp 2 ; enable TCNT & fast flags clear ; configure prescale factor to 64 ; enable OC 0 ; start an output compare operation ; with 10 ms time delay

The AD 7302 D/A Converter (1 of 2) • A dual-channel 8 -bit D/A converter made by Analog Devices • The AD 7302 converts an 8 -bit digital value into an analog voltage. • The block diagram is shown in Figure 7. 43. The AD 7302 is designed to be a memory-mapped device. The CS signal must be low for this chip to work. • The AD 7302 needs a reference voltage to operate. The reference voltage could be external one (from the REFIN pin) or the internal VDD. • Each conversion takes about 2 ms to complete.

The AD 7302 D/A Converter (2 of 2) - The output from either DAC is given by VOUTA/B = 2 × VREF × (N/256) where, N is the digital value to be converted.

Using the AD 7302 to Generate Sawtooth Waveform • Configure PB 7…PB 0, PJ 0…PJ 1 for output. • Output the digital value from 0 to 255 and repeat. For each value, pull the PJ 0 to low and then to high so that the value on pins PB 7. . PB 0 can be transferred to the AD 7302. • Pull the signal PJ 1 to low during the process.

Example 7. 10 Write a program to generate a sawtooth waveform from VOUTA pin. The assembly program is as follows: #include "c: miniidehcs 12. inc" org $1500 movb #$FF, DDRB ; configure PORTB for output bset DDRJ, $03 ; configure PJ 1~PJ 0 for output bclr PTJ, $02 ; select VOUTA output loop inc PORTB ; increase the output by one step bclr PTJ, $01 ; generate a rising edge on PJ 0 pin bset PTJ, $01 ; " bset PTJ, $01 ; add 9 more “bset” instructions to provide 2 ms bset PTJ, $01 ; for D/A conversion to complete bset PTJ, $01 ; " bset PTJ, $01 ; “ bset PTJ, $01 ; “ bra loop ; to complete the D/A conversion end The C language version of the program is on next page.

#include “c: egnu 091includehcs 12. h” void main(void) { DDRB = 0 x. FF; /* configure PORTB for output */ DDRJ |= 0 x 03; /* configure pins PJ 1~PJ 0 for output */ PTJ &= 0 x. FD; /* pull the signal A/B to low too select channel A */ while (1) { PTB += 1; PTJ &= 0 x. FE; /* generate a rising edge */ PTJ |= 0 x 01; /* “ */ PTJ |= 0 x 01; /* use dummy statements to provide 2 ms */ PTJ |= 0 x 01; /* time for D/A conversion to complete */ PTJ |= 0 x 01; PTJ |= 0 x 01; } }

Stepper Motor Control (1 of 7) • It is digital in nature and provides high degree of control. • In its simplest form, a stepper motor has a permanent magnet rotor and a stator consisting of two coils. The rotor aligns with the stator coil that is energized. • By changing the coil that is energized, the rotor is turned. • Figure 7. 45 a to 7. 45 d illustrate how the rotor rotates clockwise in full step. • By changing the energizing order as shown in Figure 7. 46, the stepper will rotate counterclockwise in full step.

Stepper Motor Control (2 of 7)

Stepper Motor Control (3 of 7)

Stepper Motor Control (4 of 7)

Stepper Motor Control (5 of 7) • In a four-pole stepper motor shown in Figure 7. 45 & 7. 46, a full step is 90 degrees. • The stepper motor may also operate with half step. A half step occurs when the rotor (in a four-pole step) is moved to eight discrete positions (45º). • To operate the stepper motor in half steps, sometimes both coils may have to be on at the same time. When two coils in close proximity are energized, there is a resultant magnetic field whose center will depend on the relative strengths of the two magnetic fields. • Figure 7. 47 illustrates the half-stepping sequence. • The step sizes of the stepper motors may vary from approximately 0. 72º to 90º. The most common step sizes are 1. 8º, 7. 5º, and 15º. • The actual stator of a real motor has more segments than previously indicated. One example is shown in Figure 7. 48.

Stepper Motor Control (6 of 7)

Stepper Motor Control (7 of 7)

Stepper Motor Drivers (1 of 6) • • Driving a step motor involves applying a series of voltages to the coils of the motor. A subset of coils is energized at a time to cause the motor to rotate one step. The pattern of coils energized must be followed exactly for the motor to work correctly. A microcontroller can easily time the duration that the coil is energized, and control the speed of the stepper motor in a precise manner. The circuit in Figure 7. 49 shows how the transistors are used to switch the current to each of the four coils of the stepper motor. The diodes in Figure 7. 49 are called fly back diodes and are used to protect the transistors from reverse bias. The transistor loads are the windings in the stepper motor. The windings are inductors, storing energy in a magnetic field. When the current is cut off, the inductor dispenses its stored energy in the form of an electric current. This current attempts to flow through the transistor, reversely biasing its collector-emitter pair. The diodes are placed to prevent this current from going through the transistors.

Stepper Motor Drivers (2 of 6)

Stepper Motor Drivers (3 of 6) • The normal full-step sequence shown in Table 7. 17 should be used for high-torque applications. • For lower-torque applications the half-step mode is used and its sequence is shown in Table 7. 18. • The microcontroller outputs the voltage pattern in the sequence shown in Table 7. 17 or 7. 18. • Table 7. 17 & 7. 18 are circular. The values may be output in the order as shown in the table, which will rotate the motor clockwise; or in the reverse order, which will rotate the motor counterclockwise. • A delay of about 5 to 15 ms is required between two steps to prevent motor from missing steps.

Stepper Motor Drivers (4 of 6)

Stepper Motor Drivers (5 of 6) • • Example 7. 11 Assuming that pins PP 3. . . PP 0 are used to drive the four transistor in Figure 7. 30, write a subroutine to rotate the stepper motor clockwise one cycle using the half-step sequence. Solution: #include "c: miniidehcs 12. inc" step 1 equ $0 A step 2 equ $08 step 3 equ $09 step 4 equ $01 step 5 equ $05 step 6 equ $04 step 7 equ $06 step 8 equ $02 half_step movb #$FF, DDRP movb #step 1, PTP bsr delay 10 ms movb #step 2, PTP bsr delay 10 ms movb #step 3, PTP bsr delay 10 ms movb #step 4, PTP ; configure PTP for output

Stepper Motor Drivers (6 of 6) movb #step 5, PTP bsr delay 10 ms movb #step 6, PTP bsr delay 10 ms movb #step 7, PTP bsr delay 10 ms movb #step 8, PTP bsr delay 10 ms movb #step 1, PTP bsr delay 10 ms rts ; the following subroutine waits for 10 ms delay 10 ms movb #$90, TSCR 1 movb #$06, TSCR 2 bset TIOS, IOS 0 ldd TCNT addd #3750 std TC 0 wait_lp 2 brclr TFLG 1, $01, wait_lp 2 rts end ; enable TCNT & fast flags clear ; configure prescale factor to 64 ; enable OC 0 ; start an output compare operation ; with 10 ms time delay 10 ms

Key Wakeups • Many embedded products are powered by battery. To lengthen the battery life, most microcontrollers have incorporated power-saving modes such as the WAIT, STOP modes. • All HCS 12 members have incorporated the key wakeup feature which would wake up the CPU when keys connected to certain input ports are pressed. • After entering the wait or stop mode, the MCU will be interrupted when one of these pins is pressed. • The port H, J, and P of the HCS 12 have implemented the keywakeup function. • The user selects the active edge for wakeup by programming the port device enable register and the port polarity select register. • The port interrupt enable register and the interrupt flag register together allow the user to wake up the MCU.

Key Wakeup Initialization • Step 1 – Set the direction of the key wakeup bits to input by writing zeros to the data direction register. • Step 2 – Select the rising edge or the falling edge of the wake up pin to interrupt the MCU by programming the related registers. • Step 4 – Write the service routine for the key wakeup interrupt and initialize the key wakeup interrupt vector. • Step 5 – Clear any flags that have been set in the key wakeup flag register. • Step 6 – Enable the key wakeup function by setting the appropriate bits in the wakeup interrupt enable register. • Step 7 – Clear the global interrupt mask (the I bit of the CCR register).

Considerations of the Key Wakeup Application • Many applications are designed to be a wait loop that waits for the user to request for service. – When a request is entered, the application calls an appropriate routine to provide the service. After the service is done, the routine returns to the wait loop. • • After the completion of a service to a user request, the application software starts a timer. If the user enters another command before the timer times out, the application software resets the timer and responds to the user request. If the timer times out before the user makes another service request, the application software puts the microcontroller in low power mode to save power. Whenever the user presses a key, an interrupt is generated to wake up the microcontroller. The service routine for the key interrupt simply clears the key wakeup flag and returns to the wait loop. Since we can choose either the rising or the falling edge to interrupt the CPU, the choice is based on whethere is pull-down or pull-up device inside the chip. If the MCU has internal pull down device, then choose the rising edge as the active edge. Otherwise, choose the falling edge as the active edge.

• Example 7. 13 Write an instruction sequence to configure Port P upper four pins for wakeup feature. Program the Port P so that pins PP 7. . . PP 4 generate interrupt whenever there is a falling edge applied to any one of these four pins. • Solution: #include “c: miniidehcs 12. inc” … bclr DDRP, $F 0 bset PERP, $F 0 bclr PPSP, $F 0 movb #$FF, PIFP bset PIEP, $F 0 cli ; configure PP<7: 4> pins for input ; enable PP 7~PP 4 pins’ pull device ; choose pull-up device ; clear the Port P key wakeup flags ; enable Port P interrupt ; enable key wakeup interrupt globally