Chapter 6 Selected Design Topics Programmable Implementation Technologies

Chapter 6 Selected Design Topics Programmable Implementation Technologies Section 6. 8

Overview § Why Programmable Logic? § Programming Technologies § Read-Only Memories (ROMs) § Programmable Logic Arrays (PLAs) § Programmable Array Logic (PALs) 2

Why Programmable Logic? § Facts: • It is most economical to produce an IC in large volumes • Many designs required only small volumes of ICs § Need an IC that can be: • Produced in large volumes • Handle many designs required in small volumes § A programmable logic part can be: • made in large volumes • programmed to implement large numbers of different low-volume designs 3

Programmable Logic - More Advantages § Many programmable logic devices are fieldprogrammable, i. e. , can be programmed outside of the manufacturing environment § Most programmable logic devices are erasable and reprogrammable. • Allows “updating” a device or correction of errors • Allows reuse the device for a different design - the ultimate in re-usability! • Ideal for course laboratories 4

Programmable Logic – Advantages (cont. ) § Programmable logic devices can be used to prototype design that will be implemented for sale in regular ICs. • Complete Intel Pentium designs were actually prototyped with specialized systems based on large numbers of VLSI programmable devices! 5

Gate Symbols Figure 6 -18 Conventional and Array Logic Symbols for OR Gate 6

ROM, PAL and PLA Configurations Fixed AND array (decoder) Inputs Programmable Connections Programmable OR array Outputs (a) Programmable Read-Only Memory (PROM) Inputs Programmable Connections Programmable AND array Fixed OR array Outputs (b) Programmable Array Logic (PAL) device Inputs Programmable Connections Programmable AND array Connections Programmable OR array Outputs (c) Programmable Logic Array (PLA) device 7

Read Only Memory Example § Example: A 8 X 4 ROM (N = 3 input lines, M= 4 output lines) § The fixed "AND" array is a “decoder” with 3 inputs and 8 X X X D 7 D 6 outputs implementing minterms. X X D 5 X D 4 § The programmable "OR“ A 2 D 3 X array uses a single line to A D 2 X X A 1 D 1 represent all inputs to an B X A 0 D 0 C OR gate. An “X” in the array corresponds to attaching the minterm to the OR § Read Example: For input (A 2, A 1, A 0) F 0 F 2 F 1 F 3 = 001, output is (F 3, F 2, F 1, F 0 ) = 0011. § What are functions F 3, F 2 , F 1 and F 0 in terms of (A 2, A 1, A 0)? 8

In General: Read Only Memory § Read Only Memories (ROM) or Programmable Read Only Memories (PROM) have: • N input lines, • M output lines, and • 2 N decoded minterms. § Fixed AND array with 2 N outputs implementing all N-literal minterms. § Programmable OR Array with M outputs lines to form up to M sum of minterm expressions. 9

In General: ROM Programmming § A “program” for a ROM or PROM is simply a “multiple-output” truth table • If a 1 entry, a connection is made to the corresponding minterm for the corresponding output • If a 0, no connection is made § Can be viewed as a “memory” with the “inputs as addresses” of “data (output values) “, hence ROM or PROM names! 10

Programmable Array Logic (PAL) § The PAL is the opposite of the ROM, having a programmable set of ANDs combined with fixed ORs. § Disadvantage • ROM guaranteed to implement any M functions of N inputs. PAL may have too few inputs to the OR gates. § Advantages • For given internal complexity, a PAL can have larger N and M • Some PALs have outputs that can be complemented, adding POS functions 11

Programmable Array Logic Example AND gates inputs 0 1 2 3 4 5 6 7 8 9 X § 4 -input, 3 -output PAL with fixed, 3 -input OR terms Product 1 term X X 2 F 1 3 I 15 A X X 7 F 2 X 6 X 5 X 4 X I 2 5 B X X X 8 F 3 X 9 I 3 5 C X X 11 X X 10 F 4 X 12 I 4 12 0 1 2 3 4 5 6 7 8 9

AND gates inputs Programmable Array Logic Example 1 2 F 1 X X 3 I 1 A X X 6 X 7 F 2 X X B X 8 F 3 X I 2 X 5 X 4 X X X 9 C X 11 F 4 X 10 X X I 3 X F 1 = A B + C F 2 = A B C + AB F 3 = F 4 = Product term 5 6 7 8 9 X § 4 -input, 4 -output PAL with fixed, 3 -input OR terms § What are the equations for F 1 through F 4? 0 1 2 3 4 12 D I 4 0 1 2 3 4 5 6 7 8 9 13

Programmable Logic Array, PLA Example § What are the equations for F 1 and F 2? § Could the PLA implement the functions without the XOR gates? Figure 6 -21 3 -input, 2 -output PLA with 4 product terms 14

Example 6 -3: Implementing a Combinational Circuit Using a PLA: 3 -input, 2 -output PLA with 4 product terms § F 1 = ∑ m(3, 5, 6, 7) § F 2 = ∑ m(1, 2, 3, 7) 5 product terms YES. YES. 4 product terms 15

Example 6 -4: Implementing a Combinational Circuit Using a PAL § W(A, B, C, D) = ∑ m(2, 13) § X(A, B, C, D) = ∑ m(7, 8, 9, 10, 11, 12, 13, 14, 15) § Y(A, B, C, D) = ∑ m(0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15) § Z(A, B, C, D) = ∑ m(1, 2, 8, 12, 13) 16

Figure 17