Chapter 6 IO PORTS 1 IO PORTS 5

Chapter 6 I/O PORTS 1

I/O PORTS § 5 ports are available. Ø Ø Ø PORT PORT A B C D E. § Some I/O pins are multiplexed with an alternate function § Each port has 3 registers for its operation. 2

I/O PORTS These registers are: § TRIS register. (Data Direction register) § PORT register § LAT register (Data Latch register) 3

Features of I/O Ports (A – D) § PORTA , PORTB, PORTC and PORTD are 8 bit wide bidirectional port. § Setting TRISA bit (= 1) will make the PORT pin an input § Clearing TRISA bit (= 0) will make PORT pin an output 4

PORTD § PORTD can also operate as an 8 -bit wide Parallel Slave Port (PSP) or microprocessor port. § PSP operation is controlled by the 4 upper bits of the TRISE register. 5

PORTE § PORTE is a 4 -bit wide port. § 3 pins (RE 0, RE 1 & RE 2) are individually configurable as inputs or outputs. § These pins have Schmitt Trigger input buffers. § When selected as an analog input, these pins will read as ‘ 0’s. § TRISE bit (= 1) will make the PORTE pin an input § TRISE bit (= 0) will make the PORTE pin an output 6

Programming Data Direction Register § TRISA = 0 x. FF or 0 b 1111 (Set all pins as INPUTS) § TRISA = 0 x 00 or 0 b 0000 (Set all pins as OUTPUTS) § TRISA = 0 x 1 F or 0 b 00011111 (pins 7, 6 & 5 as OUTPUTS 4, 3, 2, 1 & 0 as INPUTS) § TRISAbits. TRISA 1 = 1; Set pin 1 as INPUT. § TRISAbits. TRISA 2 = 0; Set pin 2 as OUTPUT. 7

Programming PORTA register § PORTA = 0 x. FF or 0 b 1111 (All pins become logic “ 1”) § PORTA = 0 x 00 or 0 b 0000 (All pins become logic “ 0”) § PORTA = 0 x 1 F or 0 b 00011111 (Pins 7, 6 & 5 as logic “ 0” and 4, 3, 2, 1 & 0 as logic “ 1”) § PORTAbits. RA 1 = 1; (Pin 1 becomes logic “ 1”) § PORTAbits. RA 2 = 0 (Pin 2 becomes logic “ 0” 8