Chapter 6 Introduction to Sequential Devices The Sequential

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Chapter 6 -- Introduction to Sequential Devices

Chapter 6 -- Introduction to Sequential Devices

The Sequential Circuit Model Figure 6. 1

The Sequential Circuit Model Figure 6. 1

State Tables and State Diagrams Figure 6. 2

State Tables and State Diagrams Figure 6. 2

Sequential Circuit Example Figure 6. 3

Sequential Circuit Example Figure 6. 3

Latch and Flip-flop Timing Figure 6. 4

Latch and Flip-flop Timing Figure 6. 4

TTL Memory Elements

TTL Memory Elements

Set Latch Figure 6. 5

Set Latch Figure 6. 5

Reset Latch Figure 6. 6

Reset Latch Figure 6. 6

Set-Reset Latch (SR latch) Figure 6. 7

Set-Reset Latch (SR latch) Figure 6. 7

NAND SR Latch Figure 6. 8

NAND SR Latch Figure 6. 8

Set-Reset Latch Timing Diagram Figure 6. 9

Set-Reset Latch Timing Diagram Figure 6. 9

SR Latch Propagation Delays

SR Latch Propagation Delays

SR Latch Characteristics Figure 6. 11 Q* = S + R Q

SR Latch Characteristics Figure 6. 11 Q* = S + R Q

SN 74279 Latch with Two Set Inputs Figure 6. 12

SN 74279 Latch with Two Set Inputs Figure 6. 12

Gated SR Latch Figure 6. 13

Gated SR Latch Figure 6. 13

Gated SR Latch Characteristics Figure 6. 14 Q* = SC + R Q +

Gated SR Latch Characteristics Figure 6. 14 Q* = SC + R Q + C Q

Delay Latch (D latch) Figure 6. 15

Delay Latch (D latch) Figure 6. 15

D Latch Characteristics Figure 6. 16 Q* = DC + C Q

D Latch Characteristics Figure 6. 16 Q* = DC + C Q

D Latch Timing Diagram Figure 6. 17

D Latch Timing Diagram Figure 6. 17

D Latch Timing Constraints Figure 6. 18

D Latch Timing Constraints Figure 6. 18

The SN 74 LS 75 D Latch Figure 6. 19

The SN 74 LS 75 D Latch Figure 6. 19

Propagation Delays and Time Constraints for the SN 74 LS 75

Propagation Delays and Time Constraints for the SN 74 LS 75

Hazard-Free D Latch, the SN 74116 Figure 6. 20 Q* = DC + C

Hazard-Free D Latch, the SN 74116 Figure 6. 20 Q* = DC + C Q + DC

Master-Slave SR Flip-flop Figure 6. 20

Master-Slave SR Flip-flop Figure 6. 20

SR Master-Slave Flip-Flop Characteristics Figure 6. 22 Q* = S + R Q

SR Master-Slave Flip-Flop Characteristics Figure 6. 22 Q* = S + R Q

Master-Slave D Flip-Flop Figure 6. 23

Master-Slave D Flip-Flop Figure 6. 23

Master-Slave D Flip-Flop Characteristics Figure 6. 24 Q* = D

Master-Slave D Flip-Flop Characteristics Figure 6. 24 Q* = D

Pulse-Triggered JK Flip-Flop Characteristics Figure 6. 25 Q* = K Q + JQ

Pulse-Triggered JK Flip-Flop Characteristics Figure 6. 25 Q* = K Q + JQ

Pulse-Triggered JK Flip Realization Figure 6. 26

Pulse-Triggered JK Flip Realization Figure 6. 26

The SN 7476 Dual Pulse-Triggered JK Flip-Flop Figure 6. 27

The SN 7476 Dual Pulse-Triggered JK Flip-Flop Figure 6. 27

SN 7474 Dual Positive-Edge-Triggered D Flip-Flop Figure 6. 28

SN 7474 Dual Positive-Edge-Triggered D Flip-Flop Figure 6. 28

SN 7474 Excitation Table Figure 6. 29

SN 7474 Excitation Table Figure 6. 29

SN 7474 Flip-Flop Timing Specifications Figure 6. 30

SN 7474 Flip-Flop Timing Specifications Figure 6. 30

SN 74175 Positive-Edge-Triggered D Flip-Flop Figure 6. 31 (a)

SN 74175 Positive-Edge-Triggered D Flip-Flop Figure 6. 31 (a)

SN 74273 Positive-Edge-Triggered D Flip-Flop Figure 6. 31 (b)

SN 74273 Positive-Edge-Triggered D Flip-Flop Figure 6. 31 (b)

SN 74 LS 73 A Edge-Triggered JK Flip-Flop Logic Diagram Figure 6. 32 (a)

SN 74 LS 73 A Edge-Triggered JK Flip-Flop Logic Diagram Figure 6. 32 (a)

SN 74 LS 73 A Logic Symbols Figure 6. 32 (b) and (c)

SN 74 LS 73 A Logic Symbols Figure 6. 32 (b) and (c)

SN 74276 and SN 74111 Edge-Triggered JK Flip-Flops Figure 6. 32 (d) and (e)

SN 74276 and SN 74111 Edge-Triggered JK Flip-Flops Figure 6. 32 (d) and (e)

Negative-Edge-Triggered T Flip-Flop Figure 6. 33

Negative-Edge-Triggered T Flip-Flop Figure 6. 33

Edge-Triggered T Flip-Flop Characteristics Figure 6. 34 Q* = Q

Edge-Triggered T Flip-Flop Characteristics Figure 6. 34 Q* = Q

Clocked T Flip-Flop Figure 6. 35

Clocked T Flip-Flop Figure 6. 35

Excitation Table for Clocked T Flip-Flops Figure 6. 36 Q* = T Q +

Excitation Table for Clocked T Flip-Flops Figure 6. 36 Q* = T Q + TQ

The Clocked T Flip-Flop Timing Diagram Figure 6. 37

The Clocked T Flip-Flop Timing Diagram Figure 6. 37

Summary of Latch and Flip-Flop Characteristics

Summary of Latch and Flip-Flop Characteristics

SE 555 Precision Timing Module Figure 6. 38

SE 555 Precision Timing Module Figure 6. 38

Astable Operation of The SE 555 Figure 6. 39

Astable Operation of The SE 555 Figure 6. 39

Monostable (One shot) Device Realization Figure 6. 40

Monostable (One shot) Device Realization Figure 6. 40

PROM-based Sequential Circuits Figure 6. 41

PROM-based Sequential Circuits Figure 6. 41

PROM-based Sequential Circuit Example Figure 6. 41

PROM-based Sequential Circuit Example Figure 6. 41

Prime Number Sequencer Figure 6. 43

Prime Number Sequencer Figure 6. 43

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