Chapter 5 The Inverter April 10 2003 Inverter

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Chapter 5 The Inverter April 10, 2003 Inverter

Chapter 5 The Inverter April 10, 2003 Inverter

Objective of This Chapter q Use Inverter to know basic CMOS Circuits Operations q

Objective of This Chapter q Use Inverter to know basic CMOS Circuits Operations q Watch for performance Index such as § Speed (Delay) § Optimal Transistor Sizing § Power Consumption Inverter

The CMOS Inverter: A First Glance V DD V in V out CL Inverter

The CMOS Inverter: A First Glance V DD V in V out CL Inverter

CMOS Inverter N Well VDD PMOS 2 l Contacts In Out Metal 1 Polysilicon

CMOS Inverter N Well VDD PMOS 2 l Contacts In Out Metal 1 Polysilicon NMOS GND Inverter

Two Inverters Share power and ground Abut cells Connect in Metal Vin Vout Vin

Two Inverters Share power and ground Abut cells Connect in Metal Vin Vout Vin Inverter

CMOS Inverter First-Order DC Analysis V DD Rp V out Rn V in =

CMOS Inverter First-Order DC Analysis V DD Rp V out Rn V in = V DD VOL = 0 VOH = VDD VM = f(Rn, Rp) Rn, Rp: Channel Resistance in Saturation Mode V in = 0 Inverter

CMOS Inverter: Transient Response V DD tp. HL = f(Ron. CL) Rp = 0.

CMOS Inverter: Transient Response V DD tp. HL = f(Ron. CL) Rp = 0. 69 Ron. CL V out CL CL Rn V in = 0 V in = V DD (a) Low-to-high (b) High-to-low Inverter

Voltage Transfer Characteristi c Inverter

Voltage Transfer Characteristi c Inverter

PMOS Load Lines IDn V +V DD GS, p I =-I D, n D,

PMOS Load Lines IDn V +V DD GS, p I =-I D, n D, p V =V +V out DD DS, p in =V IDp Vout Vin=0 IDn Vin=1. 5 VGSp=-1 V DS, p Vin=0 Vin=1. 5 V DS, p V out VGSp=-2. 5 V in = V DD +VGSp IDn = - I Dp Vout = V DD +VDSp (Vdd = 2. 5 V) Inverter

CMOS Inverter Load Characteristics Inverter

CMOS Inverter Load Characteristics Inverter

CMOS Inverter VTC VM: Vin = Vout Inverter

CMOS Inverter VTC VM: Vin = Vout Inverter

Switching Threshold as a Function of Transistor Ratio NMOS and PMOS are in Saturation

Switching Threshold as a Function of Transistor Ratio NMOS and PMOS are in Saturation Modes For r = 1, and mobility NMOS = 2 PMOS, Wp = 2 Wn Inverter

Switching Threshold as a Function of Transistor Ratio 1. 8 1. 7 1. 6

Switching Threshold as a Function of Transistor Ratio 1. 8 1. 7 1. 6 1. 5 M V (V) 1. 4 1. 3 1. 2 1. 1 1 0. 9 0. 8 10 0 10 W /W p 1 n Inverter

Simulated VTC Inverter

Simulated VTC Inverter

Impact of Process Variations 2. 5 2 Good PMOS Bad NMOS Vout(V) 1. 5

Impact of Process Variations 2. 5 2 Good PMOS Bad NMOS Vout(V) 1. 5 Nominal 1 Good NMOS Bad PMOS 0. 5 0 0 0. 5 1 1. 5 2 2. 5 Vin (V) Inverter

Propagation Delay Inverter

Propagation Delay Inverter

CMOS Inverter Propagation Delay Approach 1 Inverter

CMOS Inverter Propagation Delay Approach 1 Inverter

CMOS Inverter Propagation Delay Approach 2 Inverter

CMOS Inverter Propagation Delay Approach 2 Inverter

CMOS Inverters VDD PMOS 1. 2 mm =2 l In Out Metal 1 Polysilicon

CMOS Inverters VDD PMOS 1. 2 mm =2 l In Out Metal 1 Polysilicon NMOS GND Inverter

Transient Response ? tp = 0. 69 CL (Reqn+Reqp)/2 tp. LH tp. HL Inverter

Transient Response ? tp = 0. 69 CL (Reqn+Reqp)/2 tp. LH tp. HL Inverter

Design for Performance q Keep loading capacitances (CL) small q Increase transistor sizes (add

Design for Performance q Keep loading capacitances (CL) small q Increase transistor sizes (add CMOS gain) § Watch out for self-loading (for the previous stage)! q Increase VDD (? ? ) Inverter

Delay as a function of VDD Inverter

Delay as a function of VDD Inverter

Device Sizing (for fixed load) Self-loading effect: Intrinsic capacitances dominate Inverter

Device Sizing (for fixed load) Self-loading effect: Intrinsic capacitances dominate Inverter

NMOS/PMOS ratio tp. LH tp. HL tp b = Wp/Wn Inverter

NMOS/PMOS ratio tp. LH tp. HL tp b = Wp/Wn Inverter

Impact of Rise Time on Delay Inverter

Impact of Rise Time on Delay Inverter

Inverter Sizing Inverter

Inverter Sizing Inverter

Inverter Chain In Out CL If CL is given: - How many stages are

Inverter Chain In Out CL If CL is given: - How many stages are needed to minimize the delay? - How to size the inverters? May need some additional constraints. Inverter

Inverter Delay • Minimum length devices, L=0. 25 mm • Assume that for WP

Inverter Delay • Minimum length devices, L=0. 25 mm • Assume that for WP = 2 WN =2 W • same pull-up and pull-down currents • approx. equal resistances RN = RP • approx. equal rise tp. LH and fall tp. HL delays • Analyze as an RC network Delay (D): tp. HL = (ln 2) RNCL 2 W W tp. LH = (ln 2) RPCL Load for the next stage: Inverter

Inverter with Load Delay RW CL RW Load (CL) t p = k R

Inverter with Load Delay RW CL RW Load (CL) t p = k R WC L k is a constant, equal to 0. 69 Assumptions: no load -> zero delay Wunit = 1 Inverter

Inverter with Load CP = 2 Cunit Delay 2 W W Cint CL CN

Inverter with Load CP = 2 Cunit Delay 2 W W Cint CL CN = Cunit Load Delay = k. RW(Cint + CL) = k. RWCint + k. RWCL = k. RW Cint(1+ CL /Cint) = Delay (Internal) + Delay (Load) Inverter

Delay Formula Cint = g. Cgin with g 1 f = CL/Cgin - effective

Delay Formula Cint = g. Cgin with g 1 f = CL/Cgin - effective fanout R = Runit/W ; Cint =WCunit tp 0 = 0. 69 Runit. Cunit Inverter

Apply to Inverter Chain In Out 1 2 N CL tp = tp 1

Apply to Inverter Chain In Out 1 2 N CL tp = tp 1 + tp 2 + …+ tp. N Inverter

Optimal Tapering for Given N Delay equation has (N-1) unknowns, Cgin, 2 – Cgin,

Optimal Tapering for Given N Delay equation has (N-1) unknowns, Cgin, 2 – Cgin, N Minimize the delay, find N - 1 partial derivatives Result: Cgin, j+1/Cgin, j = Cgin, j/Cgin, j-1 Size of each stage is the geometric mean of two neighbors - Each stage has the same effective fanout (Cout/Cin) - Each stage has the same delay Inverter

Optimum Delay and Number of Stages When each stage is sized by f and

Optimum Delay and Number of Stages When each stage is sized by f and has same effective fanout f: Effective fanout of each stage: Minimum path delay Inverter

Example In C 1 Out 1 f f 2 C L= 8 C 1

Example In C 1 Out 1 f f 2 C L= 8 C 1 CL/C 1 has to be evenly distributed across N = 3 stages: Inverter

Optimum Number of Stages For a given load, CL and given input capacitance Cin

Optimum Number of Stages For a given load, CL and given input capacitance Cin Find optimal sizing f For g = 0, f = e, N = ln. F Inverter

Optimum Effective Fanout f Optimum f for given process defined by g fopt =

Optimum Effective Fanout f Optimum f for given process defined by g fopt = 3. 6 for g=1 Inverter

Impact of Self-Loading on tp No Self-Loading, g=0 With Self-Loading g=1 Inverter

Impact of Self-Loading on tp No Self-Loading, g=0 With Self-Loading g=1 Inverter

Normalized delay function of F Inverter

Normalized delay function of F Inverter

Buffer Design 1 f tp 1 64 65 2 8 18 64 3 4

Buffer Design 1 f tp 1 64 65 2 8 18 64 3 4 15 64 4 2. 8 15. 3 64 1 8 1 4 16 2. 8 8 1 N 64 22. 6 Inverter

Power Dissipation Inverter

Power Dissipation Inverter

Where Does Power Go in CMOS? Inverter

Where Does Power Go in CMOS? Inverter

Dynamic Power Dissipation Vdd Vin Vout CL Energy/transition = CL * Vdd 2 Power

Dynamic Power Dissipation Vdd Vin Vout CL Energy/transition = CL * Vdd 2 Power = Energy/transition * f = CL * Vdd 2 * f Not a function of transistor sizes! Need to reduce CL, Vdd, and f to reduce power. Inverter

Modification for Circuits with Reduced Swing Inverter

Modification for Circuits with Reduced Swing Inverter

Node Transition Activity and Power Inverter

Node Transition Activity and Power Inverter

Transistor Sizing for Minimum Energy q Goal: Minimize Energy of whole circuit § Design

Transistor Sizing for Minimum Energy q Goal: Minimize Energy of whole circuit § Design parameters: f and VDD § tp tpref of circuit with f=1 and VDD =Vref Inverter

Transistor Sizing (2) q Performance Constraint (g=1) q Energy for single Transition Inverter

Transistor Sizing (2) q Performance Constraint (g=1) q Energy for single Transition Inverter

Transistor Sizing (3) VDD=f(f) E/Eref=f(f) F=1 2 5 10 20 Inverter

Transistor Sizing (3) VDD=f(f) E/Eref=f(f) F=1 2 5 10 20 Inverter

Short Circuit Currents Inverter

Short Circuit Currents Inverter

How to keep Short-Circuit Currents Low? Short circuit current goes to zero if tfall

How to keep Short-Circuit Currents Low? Short circuit current goes to zero if tfall >> trise, but can’t do this for cascade logic, so. . . Inverter

Minimizing Short-Circuit Power Vdd =3. 3 Vdd =2. 5 Vdd =1. 5 Inverter

Minimizing Short-Circuit Power Vdd =3. 3 Vdd =2. 5 Vdd =1. 5 Inverter

Leakage Sub-threshold current one of most compelling issues in low-energy circuit design! Inverter

Leakage Sub-threshold current one of most compelling issues in low-energy circuit design! Inverter

Reverse-Biased Diode Leakage JS = 10 -100 p. A/mm 2 at 25 deg C

Reverse-Biased Diode Leakage JS = 10 -100 p. A/mm 2 at 25 deg C for 0. 25 mm CMOS JS doubles for every 9 deg C! Inverter

Subthreshold Leakage Component Inverter

Subthreshold Leakage Component Inverter

Static Power Consumption Wasted energy … Should be avoided in almost all cases, but

Static Power Consumption Wasted energy … Should be avoided in almost all cases, but could help reducing energy in others (e. g. sense amps) Inverter

Principles for Power Reduction q Prime choice: Reduce voltage! § Recent years have seen

Principles for Power Reduction q Prime choice: Reduce voltage! § Recent years have seen an acceleration in supply voltage reduction § Design at very low voltages still open question (0. 6 … 0. 9 V by 2010!) q Reduce switching activity q Reduce physical capacitance § Device Sizing: for F=20 – fopt(energy)=3. 53, fopt(performance)=4. 47 Inverter