RCC_APB 1 ENR Register is used to enable timer clock 14
RCC_APB 2 ENR Register is used to enable timer clock 15
Some of the STM 32 F 4 xx Timer Registers 16
CR 1 (Control 1) Register 17
Some of the CR 1 register bits 18
TIMx. SR Register 19
TIMx_SR (Staus) Register UIF Bit 20
TIMx counter (TIMx_CNT) 21
TIMx auto-reload register (TIMx_ARR) 22
TIM 2_CNT counter counting for 32 -bit 23
TIMx prescaler (TIMx_PSC) 24
TIMx Options for Prescaler 25
CNT, ARR and Compare registers (CCR) with Waveform Output 26
TIMx capture/compare registers (TIMx_CCRy) 27
TIMx_CCMR 1 for output option 28
TIMx_CCMR 2 for output option OCx. CE: Output compare x clear enable OCx. M: Output compare x mode The OCx. M options for output pin: 000: 001: 010: 011: 100: 101: 110: 111: bits in TIMx_CCMRy register are used to decide the output operation. Here are the Frozen Set output to active HIGH level when TIMx_CNT=TIMx_CCRy. Set output to inactive LOW level when TIMx_CNT=TIMx_CCRy. Toggle when TIMx_CNT=TIMx_CCRy. Forced LOW. Forced HIGH. PWM mode 1. (See Chapter 11) PWM mode 2. (See Chapter 11) OCx. PE: Output compare x preload enable CCx. S: Capture/Compare x selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CCx channel is configured as output 29