Chapter 4 The Von Neumann Model The LC

Chapter 4 The Von Neumann Model & The LC 3 Datapath & Control (These slides were developed in large part by Diana Palsetia at Upenn)

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. What Do We Know? Already discovered: • • • Gates (AND, OR. . ) Combinational logic circuits (decoders, mux) Memory (latches, flip-flops) Sequential logic circuits (state machines) Simple processors (programmable traffic sign) What’s next? • Apply all this to build a working processor 7 -2

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Von Neumann Model MEMORY MAR MDR INPUT Keyboard Mouse Scanner Disk OUTPUT PROCESSING UNIT ALU TEMP Monitor Printer LED Disk CONTROL UNIT PC IR 7 -3

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. LC-3 Processor Von Nuemann Model CONTROL UNIT 7 -4

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. LC-3 Data Path The data path of a computer is all the logic used to process information Filled arrow = info to be processed. Unfilled arrow = control signal. CONTROL UNIT 7 -5

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. One More Device Tri-state buffer • NOT an inverter! • Device with a special output that can take a third state (i. e. besides 0 and 1) D Q E D Q 1 0 0 1 1 1 0 0 Z 0 1 Z E Z = “high impedance” state Allows wires to be “shared” • Alternative to mux • Only one source may drive at a time! • Usually used to control data over a bus 7 -6

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Data Path Components Global bus • Set of wires that carry 16 -bit signals to many components • Inputs to bus are controlled by triangle structure called tri-state devices Ø Place signal on bus when enabled Ø Only one (16 -bit) signal should be enabled at a time Ø Control unit decides which signal “drives” the bus • Any number of components can read bus Ø Register only captures bus data if write-enabled by the control unit Memory and I/O • Control signals and data registers for memory and I/O devices Ø Memory: MAR, MDR (also control signal for read/write) Ø Input (keyboard): KBSR, KBDR Ø Output (text display): DSR, DDR 7 -7

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Memory 2 k x m array of stored bits Address • unique (k-bit) identifier of location Contents • m-bit value stored in location Basic Operations: LOAD • read a value from a memory location 0000 0001 0010 0011 0100 0101 0110 1101 1110 1111 00101101 • • • 10100010 STORE • write a value to a memory location 4 -8

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Data Path Components (cont. ) ALU • Input: register file or sign-extended bits from IR (immediate field) • Output: bus; used by… Ø Condition code registers Ø Register file Ø Memory and I/O registers Register File • Two read addresses, one write address (3 bits each) • Input: 16 bits from bus Ø Result of ALU operation or memory (or I/O) read • Outputs: two 16 -bit Ø Used by ALU, PC, memory address Ø Data for store instructions passes through ALU 7 -9

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. ALU Combinational Logic 4 -10

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Register File A bank of (nearby) memory 4 -11

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Data Path Components (contd. . ) PC and PCMUX • Three inputs to PC, controlled by PCMUX 1. Current PC plus 1 (normal operation) 2. Adder output (BR, JMP, …) 3. Bus (TRAP) MAR and MARMUX • Some inputs to MAR, controlled by MARMUX 1. Zero-extended IR[7: 0] (used for TRAP; more later) 2. Adder output (LD, ST, …) 7 - 12

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Data Path Components (cont. . ) Condition Code Logic • Looks at value (from ALU) on bus and generates N, Z, P signals • N, Z, P Registers are set only when control unit enables them Control Unit • For each stage in instruction processing decides: Ø Who drives the bus? Ø Which registers are write enabled? Ø Which operation should ALU perform? Lets Look at Instruction Processing next. . 7 - 13

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Instructions Fundamental unit of work Constituents • Opcode: operation to be performed • Operands: data/locations to be used for operation Encoded as a sequence of bits (just like data!) • Sometimes have a fixed length (e. g. , 16 or 32 bits) • Atomic: operation is either executed completely, or not at all 7 - 14

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Example: LC-3 ADD Instruction LC-3 has 16 -bit instructions. • Each instruction has a four-bit opcode, bits [15: 12]. LC-3 has eight registers (R 0 -R 7) for temporary storage. • Sources and destination of ADD are registers. “Add the contents of R 2 to the contents of R 6, and store the result in R 6. ” 4 -15

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. 4 -16

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Instruction Set Architecture ISA = All of the programmer-visible components and operations of the computer • memory organization Ø address space -- how may locations can be addressed? Ø addressability -- how many bits per location? • register set Ø how many? what size? how are they used? • instruction set Ø opcodes Ø data types Ø addressing modes ISA provides all information needed for someone that wants to write a program in machine language (or translate from a high-level language to machine language). 4 -17

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Instruction Processing FETCH instruction from mem. DECODE instruction EVALUATE ADDRESS FETCH OPERANDS EXECUTE operation STORE result 7 - 18

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Instruction Processing: FETCH Idea • Put next instruction in IR & increment PC Steps • • Load contents of PC into MAR Increment PC Send “read” signal to memory Read contents of MDR, store in IR F D EA OP EX S 7 - 19

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. FETCH in LC-3 Control Load PC into MAR (inc PC) Data CONTROL UNIT 7 - 20

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. FETCH in LC-3 Control Load PC into MAR Data Read Memory CONTROL UNIT 7 - 21

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. FETCH in LC-3 Control Load PC into MAR Data Read Memory Copy MDR into IR CONTROL UNIT 7 - 22

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Instruction Processing: DECODE Identify opcode • In LC-3, always first four bits of instruction • 4 -to-16 decoder asserts control line corresponding to desired opcode Identify operands from the remaining bits • Depends on opcode e. g. , for LDR, last six bits give offset e. g. , for ADD, last three bits name source operand #2 F D EA OP EX S 7 - 23

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. DECODE in LC-3 Decoding usually a part of the Control Unit but can be seperate CONTROL UNIT 7 - 24

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Control Unit State Diagram The control unit is a state machine. Here is part of a simplified state diagram for the LC-3: A more complete state diagram is in Appendix C. It will be more understandable after Chapter 5. 4 -25

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Instruction Processing: EVALUATE ADDRESS Compute address • For loads and stores • For control-flow instructions F D Examples • Add offset to base register (as in LDR) • Add offset to PC (as in LD and BR) EA OP EX S 7 - 26

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. EVALUATE ADDRESS in LC-3 Load/Store CONTROL UNIT 7 - 27

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Instruction Processing: FETCH OPERANDS Get source operands for operation F Examples D • Read data from register file (ADD) • Load data from memory (LDR) EA OP EX S 7 - 28

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. FETCH OPERANDS in LC-3 ADD CONTROL UNIT 7 - 29

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. FETCH OPERANDS in LC-3 LDR CONTROL UNIT 7 - 30

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Instruction Processing: EXECUTE Actually perform operation Examples • Send operands to ALU and assert ADD signal • Do nothing (e. g. , for loads and stores) F D EA OP EX S 7 - 31

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. EXECUTE in LC-3 ADD CONTROL UNIT 7 - 32

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Instruction Processing: STORE Write results to destination • Register or memory Examples • Result of ADD is placed in destination reg. • Result of load instruction placed in destination reg. • For store instruction, place data in memory Ø Set MDR Ø Assert WRITE signal to memory F D EA OP EX S 7 - 33

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. STORE in LC-3 ADD CONTROL UNIT 7 - 34

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. STORE in LC-3 LDR CONTROL UNIT 7 - 35

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. STORE in LC-3 STORE Set MDR CONTROL UNIT 7 - 36

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. STORE in LC-3 STORE Set MDR Assert “write” CONTROL UNIT 7 - 37

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Time to Complete One Instruction • It takes fixed number of clock ticks (repetition of rising or falling edge) to execute each instruction Ø The time interval between ticks is known as clock cycle Ø Thus instruction performance is measured in clock cycles • Hence the clock sequences each phase of an instruction by raising the right signals as the right time • So what determines the time between ticks i. e. the length of the clock cycle? 7 - 38

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Clocking Methodology • Defines when signals can be read and when they can be written • It is important to specify the timing of reads and writes because, if a value is written at the same time it is read, the value of read could be old, new or mix of both • All values are stored on clock edge (edge-triggered) i. e. within a defined interval of time (length of the clock cycle) • In a processor, since only memory elements can store values this means that Ø Any collection of combinational logic must have its inputs coming from a set of memory elements and its outputs written into a set of memory elements 7 - 39

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Clocking Methodology (contd. . ) • The length of the clock cycle is determined as follows: • The time necessary for the signals to reach memory element 2 defines the length of the clock cycle Ø i. e. minimum clock cycle time must be at least as great as the maximum propagation delay of the circuit 7 - 40