CHAPTER 4 SHIFT REGISTER Chapter 1 1 INTRODUCTION

CHAPTER 4 SHIFT REGISTER Chapter 1 1

INTRODUCTION: REGISTERS §An n-bit register has a group of n flip-flops and some Chapter 1 logic gates and is capable of storing n bits of information. §The flip-flops store the information while the gates control when and how new information is transferred into the register. §Some functions of register: vretrieve data from register vstore/load new data into register (serial or parallel) vshift the data within register (left or right) 2

Chapter 1 §Loading a register: transfer new information into the register. Requires a load control input. §Parallel loading: all bits are loaded simultaneously. 3

COMBINATIONS OF DATA TRANSFER METHODS SISO: Serial In, Serial Out 10110 SIPO: Serial In, Parallel Out Chapter 1 10110 4 How many clock edges are required for each operation? Registers 1. 4

COMBINATIONS OF DATA TRANSFER METHODS PISO: Parallel In, Serial Out 10110 Chapter 1 10110 PIPO: Parallel In, Parallel Out 10110 5 How many clock edges are required for each operation? Registers 1. 5

4 BIT SERIAL SHIFT LEFT REGISTER

4 BIT SERIAL SHIFT LEFT REGISTER

4 BIT SERIAL SHIFT LEFT REGISTER

4 BIT SERIAL SHIFT LEFT REGISTER Step 1, Q 3, Q 2 Q 1, Q 0 = 0001

4 BIT SERIAL SHIFT LEFT REGISTER Step 2: Q 3, Q 2 Q 1, Q 0 = 0011

4 BIT SERIAL SHIFT LEFT REGISTER Step 3 : Q 3, Q 2 Q 1, Q 0 = 0111

4 BIT SERIAL SHIFT LEFT REGISTER Step 4: Q 3, Q 2 Q 1, Q 0 = 1111

4 -bit Serial-in to Serial-out Shift Register 4 BIT SERIAL SHIFT RIGHT REGISTER

4 BIT SERIAL SHIFT RIGHT REGISTER

4 BIT SERIAL SHIFT RIGHT REGISTER

4 BIT SERIAL SHIFT RIGHT REGISTER

4 BIT SERIAL SHIFT RIGHT REGISTER Step 1: Q 3, Q 2 Q 1, Q 0 = 1000

4 BIT SERIAL SHIFT RIGHT REGISTER Step 1: Q 3, Q 2 Q 1, Q 0 = 1100

4 BIT SERIAL SHIFT RIGHT REGISTER Step 1: Q 3, Q 2 Q 1, Q 0 = 1110

4 BIT SERIAL SHIFT RIGHT REGISTER Step 1: Q 3, Q 2 Q 1, Q 0 = 1111

4 BIT PARALLEL IN SERIAL OUT SHIFT REGISTER (PISO)

4 BIT PARALLEL IN SERIAL OUT SHIFT REGISTER (PISO) Load mode: Load mode s active low device, they gives s/g to AND gate 2, 4, 6 & they become active. They pass B 0, B 1, B 2, B 3 bits to the corresponding flipflops. On the low going edge of clock the binary inputs B 0, B 1, B 2, B 3 will get loaded into the corresponding flipflops. Thus parallel loading is take place.

4 BIT PARALLEL IN SERIAL OUT SHIFT REGISTER (PISO) Shift mode: Shift mode is active high device, they gives s/g to AND gate 1, 3, 5 & they become active at that time AND gate 2, 4, 6 become inactive. Hence parallel loading is not possible therefore data shifting of data from left to right, bit by bit.

4 BIT SERIAL IN PARALLEL OUT SHIFT REGISTER (SIPO) In this operation the data is entered serially and taken out parallel. First data is loaded bit by bit Loading is complete after that o/p are enable No. of clock pulse require to load a four bit word is 4.

4 BIT SERIAL IN PARALLEL OUT SHIFT REGISTER (SIPO)

0 1 2 3 4 5 QA 0 1 0 0 QB 0 0 1 0 0 0 QC 0 0 0 1 0 0 QD 0 0 1 0 Chapter 1 Clock Pulse No 26

Chapter 1 27

4 -bit Parallel-in to Parallel-out Shift Register 4 BIT PARALLEL IN PARALLEL OUT SHIFT REGISTER (PIPO)

4 BIT PARALLEL IN PARALLEL OUT SHIFT REGISTER (PIPO) The 4 bit binary input B 0, B 1, B 2, B 3 is applied to the data input D 0, D 1, D 2, D 3 respectively. A negative clock pulse is applied the binary input will be loaded into flip flop simultaneously and loaded bit will appear at o/p side. Only one clock pulse is essential to load all the bits.

4 BIT BI-DIRECTIONAL SHIFT REGISTER

4 BIT BI-DIRECTIONAL SHIFT REGISTER M=1= Shift right operation M=1 then AND gate 1, 3, 5, 7 are enabled whereas the remaining AND gate 2, 4, 6, 8 will be disable. Data DR shifted bit by bit from FF 3 to FF 0, on the application of clock pulse. M=0=Shift left operation M=0 then AND gate 2, 4, 6, 8 are enabled whereas the remaining AND gate 1, 3, 5, 7 will be disable. Data DL shifted bit by bit from FF 0 to FF 3, on the application of clock pulse. M changed only when clock =0 otherwise data stored in the register may be altered.

UNIVERSAL SHIFT REGISTER

UNIVERSAL SHIFT REGISTER This shift register is capable of performing the following operations Parallel loading Left shifting Right shifting

Chapter 1 34

Chapter 1 An application of a shift register in serial/parallel and parallel/serial conversion used in serial communication. 35