Chapter 4 Processor Technology and Architecture Chapter 4

Chapter 4 Processor Technology and Architecture

Chapter 4 Processor Technology and Architecture Chapter Outline CPU Operation Instructions and Instruction Sets Instruction Format Clock Rate CPU Registers Word Size Enhancing Processor Performance The Physical CPU Future Trends

Chapter Goals • Describe CPU instruction and execution cycles • Explain how primitive CPS instructions are combined to form complex processing operations • Describe key CPU design features, including instruction format, word size, and clock rate • Describe the function of general-purpose and special-purpose registers • Compare and contrast CISC and RISC CPUs • Describe the principles and limitations of semiconductor-based microprocessors

Chapter Topics

CPU Operation • Control unit – Moves data and instructions between main memory and registers • Arithmetic logic unit (ALU) – Performs computation and comparison operations • Set of registers – Storage locations that hold inputs and outputs for the ALU

Actions Performed by CPU Fetch cycle CPU: • Fetches an instruction from primary storage • Increments IP to location of next instruction • Separates instruction into components – instruction code – data inputs • Stores all components in designated registers ALU: • Retrieves instruction code from register Execution • Retrieves data inputs from registers cycle • Passes data inputs through internal circuits to perform data transformation • Stores results in a register

Instructions and Instruction Sets • Instruction – Lowest-level command – A bit string, logically divided into components (op code and operands) – Three types (data movement, data transformation, sequence control) • Instruction sets – Collection of instructions that a CPU can process

Instructions An Example Format

Data Movement Instructions • Copy data (MOVE) among registers, primary storage, secondary storage, and I/O devices

Data Transformations • Implement simple Boolean operations (NOT, AND, OR, and XOR) • Implement addition (ADD) • Implement bit manipulation (SHIFT) – Logical shift – Arithmetic shift

Primitive Data Transformation Instructions

Data Transformations Logical SHIFT (end-off)

Data Transformations Logical SHIFT bit extraction

Data Transformations Arithmetic SHIFT multiplication

Sequence Control Operations • Control the next instruction to be fetched or executed • Operations – Unconditional branch – Conditional branch – Halt

Complex Processing Operations • Implemented by appropriate sequences of primitive instructions • Represent combinations of primitive processing operations • Represent a tradeoff between CPU complexity and – Programming simplicity – Program execution speed

Instruction Set Extensions • Additional instructions required when new data types are added • Some include instructions that combine data transformation with data movement

Instruction Format • Template describing op code position and length, and position, type, and length of each operand • Vary among CPUs (op code size, meaning of specific op code values, data types used as operands, length and coding format of each type of operand) • Most CPUs support multiple instructional formats

Instruction Formats Register/Immediate Register/Register/Address

Instruction Length Fixed Length Variable Length • Amount by which instruction pointer must be incremented after each fetch is constant • Simplify control unit function at expense of efficient memory use • Amount by which instruction pointer is incremented after a fetch is the length of the most recently fetched instruction • Use primary and secondary storage more efficiently

Reduced Instruction Set Computing (RISC) • Uses fixed length instructions, short instruction length, large number of generalpurpose registers • Generally avoids complex instructions, especially those that combine data movement and data transformation • Simpler but less efficient than CISC (Complex Instruction Set Computing)

Clock Rate • Number of instructions and execution cycles potentially available in a fixed time interval • Typically measured in thousands of MHz (1000 MHz = 1 GHz) • Rate of actual or average instruction execution is measured in MIPS or MFLOPS • CPU cycle time – inverse of clock rate • Wait state

CPU Registers • Primary roles – Hold data for currently executing program that is needed quickly or frequently (general-purpose registers) – Store information about currently executing program and about status of CPU (special-purpose registers)

General-Purpose Registers • Hold intermediate results and frequently needed data items • Used only by currently executing program • Implemented within the CPU; contents can be read or written quickly • Increasing their number usually decreases program execution time to a point

Special-Purpose Registers • Track processor and program status • Types – Instruction register – Instruction pointer – Program status word (PSW) • Stores results of comparison operation • Controls conditional branch execution • Indicates actual or potential error conditions

Word Size • Number of bits a CPU can process simultaneously • Increasing it usually increases CPU efficiency, up to a point • Other computer components should match or exceed it for optimal performance • Implications for system bus design and physical implementation of memory

Enhancing Processor Performance Memory caching Chapter 5 (Next Week!) Pipelining Method of organizing CPU circuitry to enable multiple instructions to execute simultaneously in different stages Branch prediction and speculative execution Ensure pipeline is kept full while executing conditional branch instructions Multiprocessing Duplicate CPUs or processor stages execute in parallel

Pipelining and Superscaling

Pipelining

Branch Prediction and Speculative Execution • Definition: Branch prediction means “guessing” the answer to a conditional instruction • Definition: Speculative execution means filling an execution pipeline based on a branch prediction • Some CPUs execute both parts of a branch at the same time. – When the branch condition is evaluated, work on the “incorrect” branch is abandoned

Range of Possible Approaches for Multiprocessing • Duplicate circuitry for some or all processing stages within a single CPU • Duplicate CPUs implemented as separate microprocessors sharing main memory and a single system bus • Duplicate CPUs on a single microprocessor that also contains main memory caches and a special bus to interconnect the CPUs

Technology Focus Intel Pentium Processor Family • The Pentium processor was introduced in 1993 and has been upgraded several times – – – Pentium Pentium Pro MMX II III 4 Xeon

The Physical CPU • Electrical device implemented as siliconbased microprocessor • Contains millions of switches, which perform basic processing functions • Physical implementation of switches and circuits

Switches and Gates • Basic building blocks of computer processing circuits • Electronic switches – Control electrical current flow in a circuit – Implemented as transistors • Gates – An interconnection of switches – A circuit that can perform a processing function on an individual binary electrical signal, or bit

Basic Digital Gates

Basic Adder Circuits

Electrical Properties Conductivity Resistance Heat Speed and circuit length Ability of an element to enable electron flow Loss of electrical power that occurs within a conductor Negative effects of heat: • Physical damage to conductor • Changes to inherent resistance of conductor Dissipate heat with a heat sink Time required to perform a processing operation is a function of length of circuit and speed of light Reduce circuit length for faster processing

Dissipating Heat with a Heat Sink

Processor Fabrication • Performance and reliability of processors has increased with improvements in materials and fabrication techniques – Transistors and integrated circuits (ICs) – Microchips and microprocessors • First microprocessor (1971) – 2, 300 transistor • Current memory chip – 300 million transistors

The Intel 4004 Microprocessor

Microprocessors • Use small circuit size, low-resistance materials, and heat dissipation to ensure fast and reliable operation • Fabricated using expensive processes based on ultraviolet or laser etching and chemical deposition

Current Technology Capabilities and Limitations • Moore’s Law – Rate of increase in transistor density on microchips doubles every 18 -24 months with no increase in unit cost • Rock’s Law – Cost of fabrication facilities for chip generation doubles every four years • Increased packing density • Electrical resistance

Moores’s Law Doubles in 18 -24 Months

Packing Density

Future Trends • Semiconductors are approaching fundamental physical size limits • Technologies that may improve performance beyond semiconductor limitations – Optical processing – Hybrid optical-electrical processing – Quantum processing

Optical Processing • Could eliminate interconnection and simplify fabrication problems; photon pathways can cross without interfering with one another • Eliminating wires would improve fabrication cost and reliability • Not enough economic incentive to be a reality yet

Electro-Optical Processing • Devices provide interface between semiconductor and purely optical memory and storage devices – Gallium arsenide • both optical and electrical properties – Silicon-based semiconductor devices • encode data in externally generated laser light

Quantum Processing • Uses quantum states to simultaneously encode two values per bit (qubit) • Uses quantum processing devices to perform computations • Theoretically well-suited to solving problems that require massive amounts of computation

Summary • • CPU operation Instruction set and format Clock rate Registers Word size Physical implementation Future trends

Chapter Goals • Describe CPU instruction and execution cycles • Explain how primitive CPS instructions are combined to form complex processing operations • Describe key CPU design features, including instruction format, word size, and clock rate • Describe the function of general-purpose and special-purpose registers • Compare and contrast CISC and RISC CPUs • Describe the principles and limitations of semiconductor-based microprocessors