Chapter 4 ISA 1 The Von Neumann Model

Chapter 4 - ISA 1. The Von Neumann Model

The Stored Program Computer 1943: ENIAC • Presper Eckert and John Mauchly -- first general electronic computer. (or was it John V. Atanasoff in 1939? ) • Hard-wired program -- settings of dials and switches. 1944: Beginnings of EDVAC • among other improvements, includes program stored in memory 1945: John von Neumann • wrote a report on the stored program concept, known as the First Draft of a Report on EDVAC The basic structure proposed in the draft became known as the “von Neumann machine” (or model). • a memory, containing instructions and data • a processing unit, for performing arithmetic and logical operations • a control unit, for interpreting instructions For more history, see http: //www. maxmon. com/history. htm http: //www. webmienphi. com/mydocuments/TH 2. aspx 4 -2

Von Neumann Model 4 -3

Memory 2 k x m array of stored bits Address • unique (k-bit) identifier of location Contents • m-bit value stored in location Basic Operations: LOAD • read a value from a memory location 0000 0001 0010 0011 0100 0101 0110 1101 1110 1111 00101101 • • • 10100010 STORE • write a value to a memory location 4 -4

Interface to Memory How does processing unit get data to/from memory? MAR: Memory Address Register MDR: Memory Data Register To LOAD a location (A): 1. Write the address (A) into the MAR. 2. Send a “read” signal to the memory. 3. Read the data from MDR. To STORE a value (X) to a location (A): 1. Write the data (X) to the MDR. 2. Write the address (A) into the MAR. 3. Send a “write” signal to the memory. 4 -5

Processing Unit Functional Units • ALU = Arithmetic and Logic Unit • could have many functional units. some of them special-purpose (multiply, square root, …) • LC-3 performs ADD, AND, NOT Registers • Small, temporary storage • Operands and results of functional units • LC-3 has eight registers (R 0, …, R 7), each 16 bits wide Word Size • number of bits normally processed by ALU in one instruction • also width of registers • LC-3 is 16 bits 4 -6

Input and Output Devices for getting data into and out of computer memory Each device has its own interface, usually a set of registers like the memory’s MAR and MDR • LC-3 supports keyboard (input) and monitor (output) • keyboard: data register (KBDR) and status register (KBSR) • monitor: data register (DDR) and status register (DSR) Some devices provide both input and output • disk, network Program that controls access to a device is usually called a driver. 4 -7

Control Unit Orchestrates execution of the program Instruction Register (IR) contains the current instruction. Program Counter (PC) contains the address of the next instruction to be executed. Control unit: • reads an instruction from memory Ø the instruction’s address is in the PC • interprets the instruction, generating signals that tell the other components what to do Ø an instruction may take many machine cycles to complete 4 -8

Instruction Processing Fetch instruction from memory Decode instruction Evaluate address Fetch operands from memory Execute operation Store result 4 -9

Instruction The instruction is the fundamental unit of work. Specifies two things: • opcode: operation to be performed • operands: data/locations to be used for operation An instruction is encoded as a sequence of bits. (Just like data!) • Often, but not always, instructions have a fixed length, such as 16 or 32 bits. • Control unit interprets instruction: generates sequence of control signals to carry out operation. • Operation is either executed completely, or not at all. A computer’s instructions and their formats is known as its Instruction Set Architecture (ISA). 4 -10

Example: LC-3 ADD Instruction LC-3 has 16 -bit instructions. • Each instruction has a four-bit opcode, bits [15: 12]. LC-3 has eight registers (R 0 -R 7) for temporary storage. • Sources and destination of ADD are registers. “Add the contents of R 2 to the contents of R 6, and store the result in R 6. ” 4 -11

Example: LC-3 LDR Instruction Load instruction -- reads data from memory Base + offset mode: • add offset to base register -- result is memory address • load from memory address into destination register “Add the value 6 to the contents of R 3 to form a memory address. Load the contents of that memory location to R 2. ” 4 -12

Instruction Processing: FETCH Load next instruction (at address stored in PC) from memory into Instruction Register (IR). • Copy contents of PC into MAR. • Send “read” signal to memory. • Copy contents of MDR into IR. Then increment PC, so that it points to the next instruction in sequence. • PC becomes PC+1. F D EA OP EX S 4 -13

Instruction Processing: DECODE First identify the opcode. • In LC-3, this is always the first four bits of instruction. • A 4 -to-16 decoder asserts a control line corresponding to the desired opcode. F D Depending on opcode, identify other operands from the remaining bits. EA • Example: Ø for LDR, last six bits is offset Ø for ADD, last three bits is source operand #2 OP EX S 4 -14

Instruction Processing: EVALUATE ADDRESS For instructions that require memory access, compute address used for access. F Examples: D • add offset to base register (as in LDR) • add offset to PC • add offset to zero EA OP EX S 4 -15

Instruction Processing: FETCH OPERANDS Obtain source operands needed to perform operation. F Examples: D • load data from memory (LDR) • read data from register file (ADD) EA OP EX S 4 -16

Instruction Processing: EXECUTE Perform the operation, using the source operands. F Examples: D • send operands to ALU and assert ADD signal • do nothing (e. g. , for loads and stores) EA OP EX S 4 -17

Instruction Processing: STORE RESULT Write results to destination. (register or memory) F Examples: D • result of ADD is placed in destination register • result of memory load is placed in destination register • for store instruction, data is stored to memory Ø write address to MAR, data to MDR Ø assert WRITE signal to memory EA OP EX S 4 -18

Changing the Sequence of Instructions In the FETCH phase, we increment the Program Counter by 1. What if we don’t want to always execute the instruction that follows this one? • examples: loop, if-then, function call Need special instructions that change the contents of the PC. These are called control instructions. • jumps are unconditional -- they always change the PC • branches are conditional -- they change the PC only if some condition is true (e. g. , the result of an ADD is zero) 4 -19

Example: LC-3 JMP Instruction Set the PC to the value contained in a register. This becomes the address of the next instruction to fetch. “Load the contents of R 3 into the PC. ” 4 -20

Instruction Processing Summary Instructions look just like data -- it’s all interpretation. Three basic kinds of instructions: • computational instructions (ADD, AND, …) • data movement instructions (LD, ST, …) • control instructions (JMP, BRnz, …) Six basic phases of instruction processing: F D EA OP EX S • not all phases are needed by every instruction • phases may take variable number of machine cycles 4 -21

Control Unit State Diagram The control unit is a state machine. Here is part of a simplified state diagram for the LC-3: A more complete state diagram is in Appendix C. It will be more understandable after Chapter 5. 4 -22

2. The LC-3

Instruction Set Architecture ISA = All of the programmer-visible components and operations of the computer • memory organization Ø address space -- how may locations can be addressed? Ø addressibility -- how many bits per location? • register set Ø how many? what size? how are they used? • instruction set Ø opcodes Ø data types Ø addressing modes ISA provides all information needed for someone that wants to write a program in machine language (or translate from a high-level language to machine language). 4 -24

LC-3 Overview: Memory and Registers Memory • address space: 216 locations (16 -bit addresses) • addressability: 16 bits Registers • temporary storage, accessed in a single machine cycle Ø accessing memory generally takes longer than a single cycle • eight general-purpose registers: R 0 - R 7 Ø each 16 bits wide Ø how many bits to uniquely identify a register? • other registers Ø not directly addressable, but used by (and affected by) instructions Ø PC (program counter), condition codes 4 -25

LC-3 Overview: Instruction Set Opcodes • • • 15 opcodes Operate instructions: ADD, AND, NOT Data movement instructions: LD, LDI, LDR, LEA, STR, STI Control instructions: BR, JSR/JSRR, JMP, RTI, TRAP some opcodes set/clear condition codes, based on result: Ø N = negative, Z = zero, P = positive (> 0) Data Types • 16 -bit 2’s complement integer Addressing Modes • How is the location of an operand specified? • non-memory addresses: immediate, register • memory addresses: PC-relative, indirect, base+offset 4 -26

Operate Instructions Only three operations: ADD, AND, NOT Source and destination operands are registers • These instructions do not reference memory. • ADD and AND can use “immediate” mode, where one operand is hard-wired into the instruction. Will show dataflow diagram with each instruction. • illustrates when and where data moves to accomplish the desired operation 4 -27

NOT (Register) Note: Src and Dst could be the same register. 4 -28

ADD/AND (Register) this zero means “register mode” 4 -29

ADD/AND (Immediate) this one means “immediate mode” Note: Immediate field is sign-extended. 4 -30

Using Operate Instructions With only ADD, AND, NOT… • How do we subtract? • How do we OR? • How do we copy from one register to another? • How do we initialize a register to zero? 4 -31

Data Movement Instructions Load -- read data from memory to register • LD: PC-relative mode • LDR: base+offset mode • LDI: indirect mode Store -- write data from register to memory • ST: PC-relative mode • STR: base+offset mode • STI: indirect mode Load effective address -- compute address, save in register • LEA: immediate mode • does not access memory 4 -32

PC-Relative Addressing Mode Want to specify address directly in the instruction • But an address is 16 bits, and so is an instruction! • After subtracting 4 bits for opcode and 3 bits for register, we have 9 bits available for address. Solution: • Use the 9 bits as a signed offset from the current PC. 9 bits: Can form any address X, such that: Remember that PC is incremented as part of the FETCH phase; This is done before the EVALUATE ADDRESS stage. 4 -33

LD (PC-Relative) 4 -34

ST (PC-Relative) 4 -35

Indirect Addressing Mode With PC-relative mode, can only address data within 256 words of the instruction. • What about the rest of memory? Solution #1: • Read address from memory location, then load/store to that address. First address is generated from PC and IR (just like PC-relative addressing), then content of that address is used as target for load/store. 4 -36

LDI (Indirect) 4 -37

STI (Indirect) 4 -38

Base + Offset Addressing Mode With PC-relative mode, can only address data within 256 words of the instruction. • What about the rest of memory? Solution #2: • Use a register to generate a full 16 -bit address. 4 bits for opcode, 3 for src/dest register, 3 bits for base register -- remaining 6 bits are used as a signed offset. • Offset is sign-extended before adding to base register. 4 -39

LDR (Base+Offset) 4 -40

STR (Base+Offset) 4 -41

Load Effective Address Computes address like PC-relative (PC plus signed offset) and stores the result into a register. Note: The address is stored in the register, not the contents of the memory location. 4 -42

LEA (Immediate) 4 -43

Example Address Instruction Comments x 30 F 6 111000111101 R 1 PC – 3 = x 30 F 4 x 30 F 7 0001010001101110 R 2 R 1 + 14 = x 3102 x 30 F 8 0011010111111011 M[PC - 5] R 2 M[x 30 F 4] x 3102 x 30 F 9 01010100000 R 2 0 x 30 FA 00010100101 R 2 + 5 = 5 x 30 FB 011101001110 M[R 1+14] R 2 M[x 3102] 5 1010011111110111 R 3 M[M[x 30 F 4]] R 3 M[x 3102] R 3 5 x 30 FC opcode 4 -44

Control Instructions Used to alter the sequence of instructions (by changing the Program Counter) Conditional Branch • branch is taken if a specified condition is true Ø signed offset is added to PC to yield new PC • else, the branch is not taken Ø PC is not changed, points to the next sequential instruction Unconditional Branch (or Jump) • always changes the PC TRAP • changes PC to the address of an OS “service routine” • routine will return control to the next instruction (after TRAP) 4 -45

Condition Codes LC-3 has three condition code registers: N -- negative Z -- zero P -- positive (greater than zero) Set by any instruction that writes a value to a register (ADD, AND, NOT, LDR, LDI, LEA) Exactly one will be set at all times • Based on the last instruction that altered a register 4 -46

Branch Instruction Branch specifies one or more condition codes. If the set bit is specified, the branch is taken. • PC-relative addressing: target address is made by adding signed offset (IR[8: 0]) to current PC. • Note: PC has already been incremented by FETCH stage. • Note: Target must be within 256 words of BR instruction. If the branch is not taken, the next sequential instruction is executed. 4 -47

BR (PC-Relative) What happens if bits [11: 9] are all zero? All one? 4 -48

Using Branch Instructions Compute sum of 12 integers. Numbers start at location x 3100. Program starts at location x 3000. R 1 x 3100 R 3 0 R 2 12 R 2=0? NO R 4 M[R 1] R 3+R 4 R 1+1 R 2 -1 YES 4 -49

Sample Program Address Instruction Comments x 3000 111000101111 R 1 x 3100 (PC+0 x. FF) x 3001 0101011011100000 R 3 0 x 3002 01010100000 R 2 0 x 3003 00010101100 R 2 12 x 3004 0000010000000101 If Z, goto x 300 A (PC+5) x 3005 01101000000 Load next value to R 4 x 3006 0001011011000001 Add to R 3 x 3007 0001001001100001 Increment R 1 (pointer) X 3008 00010111111 Decrement R 2 (counter) x 3009 000011111010 Goto x 3004 (PC-6) 4 -50

JMP (Register) Jump is an unconditional branch -- always taken. • Target address is the contents of a register. • Allows any target address. 4 -51

TRAP Calls a service routine, identified by 8 -bit “trap vector. ” vector routine x 23 input a character from the keyboard x 21 output a character to the monitor x 25 halt the program When routine is done, PC is set to the instruction following TRAP. (We’ll talk about how this works later. ) 4 -52

Another Example Count the occurrences of a character in a file • Program begins at location x 3000 • Read character from keyboard • Load each character from a “file” Ø File is a sequence of memory locations Ø Starting address of file is stored in the memory location immediately after the program • If file character equals input character, increment counter • End of file is indicated by a special ASCII value: EOT (x 04) • At the end, print the number of characters and halt (assume there will be less than 10 occurrences of the character) A special character used to indicate the end of a sequence is often called a sentinel. • Useful when you don’t know ahead of time how many times to execute a loop. 4 -53

Flow Chart 4 -54

Program (1 of 2) Address Instruction Comments x 3000 01010100000 R 2 0 (counter) x 3001 00100110000 R 3 M[x 3012] (ptr) x 3002 111100000011 Input to R 0 (TRAP x 23) x 3003 0110001011000000 R 1 M[R 3] x 3004 0001100001111100 R 4 R 1 – 4 (EOT) x 3005 000001000 If Z, goto x 300 E x 3006 1001001001111111 R 1 NOT R 1 x 3007 0001001001100001 R 1 + 1 X 3008 0001001001000000 R 1 + R 0 x 3009 000010100001 If N or P, goto x 300 B 4 -55

Program (2 of 2) Address Instruction Comments x 300 A 00010100001 R 2 + 1 x 300 B 0001011011100001 R 3 + 1 x 300 C 0110001011000000 R 1 M[R 3] x 300 D 000011110110 Goto x 3004 x 300 E 00100000100 R 0 M[x 3013] x 300 F 00010000010 R 0 + R 2 x 3010 11110000001 Print R 0 (TRAP x 21) x 3011 1111000000100101 HALT (TRAP x 25) X 3012 Starting Address of File x 3013 00000110000 ASCII x 30 (‘ 0’) 4 -56

LC-3 Data Path Revisited Filled arrow = info to be processed. Unfilled arrow = control signal. 4 -57

Data Path Components Global bus • special set of wires that carry a 16 -bit signal to many components • inputs to the bus are “tri-state devices, ” that only place a signal on the bus when they are enabled • only one (16 -bit) signal should be enabled at any time Ø control unit decides which signal “drives” the bus • any number of components can read the bus Ø register only captures bus data if it is write-enabled by the control unit Memory • Control and data registers for memory and I/O devices • memory: MAR, MDR (also control signal for read/write) 4 -58

Data Path Components ALU • Accepts inputs from register file and from sign-extended bits from IR (immediate field). • Output goes to bus. Ø used by condition code logic, register file, memory Register File • Two read addresses (SR 1, SR 2), one write address (DR) • Input from bus Ø result of ALU operation or memory read • Two 16 -bit outputs Ø used by ALU, PC, memory address Ø data for store instructions passes through ALU 4 -59

Data Path Components PC and PCMUX • Three inputs to PC, controlled by PCMUX 1. PC+1 – FETCH stage 2. Address adder – BR, JMP 3. bus – TRAP (discussed later) MAR and MARMUX • Two inputs to MAR, controlled by MARMUX 1. Address adder – LD/ST, LDR/STR 2. Zero-extended IR[7: 0] -- TRAP (discussed later) 4 -60

Data Path Components Condition Code Logic • Looks at value on bus and generates N, Z, P signals • Registers set only when control unit enables them (LD. CC) Ø only certain instructions set the codes (ADD, AND, NOT, LDI, LDR, LEA) Control Unit – Finite State Machine • On each machine cycle, changes control signals for next phase of instruction processing Ø who drives the bus? (Gate. PC, Gate. ALU, …) Ø which registers are write enabled? (LD. IR, LD. REG, …) Ø which operation should ALU perform? (ALUK) Ø… • Logic includes decoder for opcode, etc. 4 -61