Chapter 3 The concept of the signal Process

Chapter 3 ä The concept of the signal ä Process concurrency ä Delta time ä Concurrent and sequential statements ä Process activation by a signal event ä Signal-valued & signal-related attributes ä Exercises 26 -Feb-21 EE 514 1

The concept of the signal Signal functions as connection line which transfers information between circuit parts ØSignal properties • present and future values • timing delay • event and transaction • signal driver and signal resolution ØMultiple drivers 26 -Feb-21 EE 514 2

Process concurrency ä NANXOR code 26 -Feb-21 EE 514 entity NANDXOR is port ( A, B : in bit; C : in bit; D : out bit); end NANDXOR; architecture RTL of NANDXOR is signal T : bit; begin p 0 : T <= A nand B after 2 ns; p 1 : process (T, C) begin D <= T xor C after 3 ns; end process p 1; end RTL; 3

Process concurrency Signal T: bit; Defines T as the connection signal between NAND and OR gates. Initialization: signals set to their default (left most for their type) values Each process is evaluated and then suspended Active Signal event Suspended Update signal value Select a process by a scheduler 26 -Feb-21 EE 514 Running Execution complete 4

Process concurrency architecture RTL of NANDXOR is signal T : bit; begin p 0 : T <= A nand B after 2 ns; p 1 : process (T, C) begin D <= T xor C after 3 ns; end process p 1; end RTL; 26 -Feb-21 EE 514 5

Delta time architecture DELTA of NANDXOR is signal T : bit; begin p 0 : T <= A nand B; p 1 : process (T, C) begin D <= T xor C; end process p 1; end DELTA; 26 -Feb-21 EE 514 6

Delta time ä Compare Figures 3. 5 & 3. 6 26 -Feb-21 EE 514 7

Delta time ä Waveforms at time 30 26 -Feb-21 EE 514 8

Delta time Processes p 0, p 1 have no time delay, but if the simulator continues to increase the delta delay, the delta goes up infinitely and the simulator may go into an infinite loop. 26 -Feb-21 EE 514 9

Concurrent & sequential statements ä Concurrent statements ä block statement process statement generate statement procedure call statement assert statement signal assignment component instantiation if statement case and loop statements procedure call statement assert statement signal assignment statement variable assignment statement null, exit, and wait statements return and next statements 26 -Feb-21 EE 514 Sequential statements 10

Concurrent & sequential statements VHDL coding rules ä ä Only concurrent statements can be inside the architecture statement part. Sequential statements can only appear inside the procedure and function body and inside the process statement. Signals are used to communicate among concurrent processes. Local variables can only be declared inside the procedure and function body and the process statement. They are not visible outside of the procedure, function, and process statement. 26 -Feb-21 EE 514 11

Concurrent & sequential statements ä Architecture VHDL code entity OVERALL is end OVERALL architecture RTL of OVERALL is --architecture declarative part begin --architecture statement part end RTL; 26 -Feb-21 EE 514 12

Concurrent & sequential statements 26 -Feb-21 EE 514 13

Process activation by a signal event architecture SLIST of NANDXOR is signal T : bit; begin p 0 : T <= A nand B; p 1 : process (T) begin D <= T xor C; end process p 1; end SLIST; 26 -Feb-21 EE 514 14

Process activation by a signal event T is the sensitivity list of the p 1 process (line 5 of SLIST architecture). Process is activated by a signal T event. A process statement requires an explicit wait statement or a process sensitivity list but not both. 26 -Feb-21 EE 514 15

Process activation by a signal event Wrong simulation waveforms of the SLIST 26 -Feb-21 EE 514 16

Signal-valued & signal-related attributes ä ä SIG’delayed(T) defines a signal which is the signal SIG delayed by time T. T=0 ns is the default if parameter T is not specified. SIG’stable(T) defines a BOOLEAN signal whose value is TRUE if signal SIG has not had an event for the length of time T. T=0 ns is the default if parameter T is not specified. SIG’stable would be FALSE during the simulation cycle when SIG is changed and then returns to TRUE. 26 -Feb-21 EE 514 17

Signal-valued & signal-related attributes ä ä SIG’quiet(T) defines a BOOLEAN signal whose value is TRUE if signal SIG has not had an transaction (not active) for the length of time T. T=0 ns is the default. SIG’quiet would be FALSE during the simulation cycle when SIG is assigned to and then returns to TRUE. SIG’transaction defines a BIT signal whose value toggles each time a transaction occurs on signal SIG. 26 -Feb-21 EE 514 18

Signal-valued & signal-related attributes ä ä ä SIG’event is a BOOLEAN typed attribute. It is true if an event occurs on signal SIG during the current simulation cycle. SIG’active is a BOOLEAN typed attribute. It is true if a tranction occurs on signal SIG during the current simulation cycle. SIG’last_event is a TIME typed attribute. It returns the amount of time elapsed since the last event on signal SIG. 26 -Feb-21 EE 514 19

Signal-valued & signal-related attributes ä ä SIG’last_active is a TIME typed attribute. It returns the amount of time elapsed since the last transaction on signal SIG’last_value returns the value of signal SIG before the last event on signal SIG. 26 -Feb-21 EE 514 20

Exercises Is it possible for a VHDL simulator to run forever without advancing simulation time? For example, Figure 3. 13 shows a NAND gate with its output connecting to one of its inputs architecture RTL of RUNAWAY is signal T : bit; begin T <= X nand T; Z <= T; end RTL; entity RUNAWAY is port ( X : in bit; Z : out bit); end RUNAWAY; 26 -Feb-21 EE 514 21