Chapter 3 System Buses Yonsei University Contents 3

Chapter 3 System Buses Yonsei University

Contents • • • 3 -2 Computer Components Computer Function Interconnection Structures Bus Interconnection PCI Recommended Reading & Web sites Yonsei University

Program Concept Computer components • Hardwired systems are inflexible • General purpose hardware can do different tasks, given correct control signals • Instead of re-wiring, supply a new set of control signals 3 -3 Yonsei University

What Is A Program? Computer components • A sequence of steps • For each step, an arithmetic or logical operation is done • For each operation, a different set of control signals is needed 3 -4 Yonsei University

Function of Control Unit Computer components • For each operation a unique code is provided – e. g. ADD, MOVE • A hardware segment accepts the code and issues the control signals • We have a computer! 3 -5 Yonsei University

Hardware & Software Approaches 3 -6 Computer components Yonsei University

Computer Components Computer components • Programming is now much easier • To distinguish this new method of programming, a sequence of codes or instruction is called software • Instruction interpreter & a module of general-purpose arithmetic and logic functions 3 -7 Yonsei University

Components Computer components • The process of connecting together the various components in the desired configuration as a form of programming • The resulting “program” is in the form of hardware and is termed a hardwired program • The system accepts data and produces results • For each step, a new set of control signals is needed 3 -8 Yonsei University

Components Computer components • The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit • Data and instructions need to get into the system and results out – Input/output • Temporary storage of code and results is needed – Main memory 3 -9 Yonsei University

Computer Components: Top Level View 3 -10 Yonsei University Computer components

Computer function Basic Instruction Cycle • Two steps: – Fetch – Execute 3 -11 Yonsei University

Instruction Fetch & Execute Computer function • Program Counter (PC) holds address of next instruction to fetch • Processor fetches instruction from memory location pointed to by PC • Increment PC (Unless told otherwise) • Instruction loaded into Instruction Register (IR) • Instruction contains bits to act of processor • Processor interprets instruction and performs required actions 3 -12 Yonsei University

Computer function Execute Cycle • Processor-memory – data transfer between CPU and main memory • Processor I/O – Data transfer between CPU and I/O module • Data processing – Some arithmetic or logical operation on data • Control – Alteration of sequence of operations – e. g. jump • Combination of above 3 -13 Yonsei University

Characteristics of A Hypothetical Machine 3 -14 Yonsei University Computer function

Example of Program Execution 3 -15 Computer function Yonsei University

Computer function Instruction Fetch & Execute • With a more complex set of instruction, need fewer cycle • Modern processor include instruction of containing more than one address • Execution cycle for a particular instruction involve more than one reference to memory 3 -16 Yonsei University

Instruction Cycle State Diagram 3 -17 Computer function Yonsei University

Instruction Cycle State Computer function • Instruction address calculation (iac) – Determine the address of the next instruction to be executed • Instruction fetch (if) – Read instruction from its memory location into the processor • Instruction operation decoding (iod) – Analyze instruction to determine type of operation to be performed & operands to be used • Operand address calculation (aoc) – Determine the address of operand (If operation involve reference to an operand in memory or I/O module 3 -18 Yonsei University

Computer function Instruction Cycle State • Operand fetch (of) – Fetch the operand from memory or read it from I/O • Data operation (do) – Perform the operation indicated in the instruction • Operand store (os) – Write the result into memory or out to I/O 3 -19 Yonsei University

Computer function Instruction Cycle State • Single Instruction specify an operation to be performed on a vector of numbers or a string of characters (on some machines) 3 -20 Yonsei University

Computer function Interrupts • Mechanism by which other modules (e. g. I/O) may interrupt normal sequence of processing • Interrupts provided to improve processing efficiency • I/O program consists of three sections – A sequence of instruction to prepare actual I/O operation – The actual I/O command – A sequence of instruction to complete operation 3 -21 Yonsei University

Class of Interrupts Computer function Program Generated by some condition occurs as a result of an instruction execution such as arithmetic overflow division by zero, attempt to execute an illegal machine instruction, and reference outside a user’s allowed memory space Timer Generated by a timer within the processor. This allows the operating system to perform certain functions on a regular basis I/O Generated by an I/O controller, to signal normal completion of an operation or to signal a variety of error conditions Hardware failure Generated by a failure such as power failure or memory parity error 3 -22 Yonsei University

Interrupts & The Instruction Cycle • Processor engaged in executing other instructions while I/O operation is in progress (With interrupts) 3 -23 Yonsei University Computer function

Computer function Program Flow Control 3 -24 Yonsei University

Transfer of Control Via Interrupts Computer function • Processor and operation system are responsible for suspending user program and resuming at the same point 3 -25 Yonsei University

Transfer of Control Via Interrupts 3 -26 Yonsei University Computer function

Interrupt Cycle Computer function • Added to instruction cycle • Processor checks for interrupt – Indicated by an interrupt signal • If no interrupt, fetch next instruction • If interrupt pending processor does: – – – 3 -27 Suspend execution of current program Save context Set PC to start address of interrupt handler routine Process interrupt Restore context and continue interrupted program Yonsei University

Instruction Cycle With Interrupts 3 -28 Computer function Yonsei University

Program Timing: Short I/O Wait Computer function • Less than time to complete execution of instructions between write operations in user program 3 -29 Yonsei University

Program Timing: Short I/O Wait 3 -30 Computer function Yonsei University

Computer function Program Timing: Long I/O Wait • User program reaches second WRITE call before I/O operation spawned by the first call is complete • User program is hung up at that point 3 -31 Yonsei University

Computer function Program Timing: Long I/O Wait • Gain efficiency because of time during which I/O operation underway overlaps with execution of user instructions 3 -32 Yonsei University

Program Timing: Long I/O Wait 3 -33 Computer function Yonsei University

Instruction Cycle (with Interrupts) - State Diagram 3 -34 Yonsei University Computer function

Multiple Interrupts Computer function • Two approaches to dealing with multiple interrupts • The first to disable interrupts while interrupt being processed – Nice & simple, Interrupts handled in strict sequential order – Drawback : Do not take into account relative priority or time-critical needs 3 -35 Yonsei University

Computer function Multiple Interrupts - Sequential 3 -36 Yonsei University

Computer function Multiple Interrupts - Sequential • Second to define priories for interrupts and to allow interrupt of higher priority to cause lower-priority interrupt handler to be itself interrupted 3 -37 Yonsei University

Multiple Interrupts - Nested 3 -38 Computer function Yonsei University

Multiple Interrupts Computer function • Disable interrupts – Processor will ignore further interrupts whilst processing one interrupt – Interrupts remain pending and are checked after first interrupt has been processed – Interrupts handled in sequence as they occur • Define priorities – Low priority interrupts can be interrupted by higher priority interrupts – When higher priority interrupt has been processed, processor returns to previous interrupt 3 -39 Yonsei University

Computer function Example Time Sequence of Multiple Interrupts 3 -40 Yonsei University

Computer function I/O Function • I/O module exchange data directly with the processor • Desirable to allow I/O exchanges to occur directly with memory – In some cases 3 -41 Yonsei University

Interconnection Structures Interconnection structures • Collection of paths connecting various modules called interconnection structure • All the units must be connected • Different type of connection for different type of unit – Memory – Input/Output – CPU 3 -42 Yonsei University

Interconnection structures Memory Connection • Receives and sends data • Receives addresses (of locations) • Receives control signals – Read – Write – Timing 3 -43 Yonsei University

Input/Output Connection Interconnection structures • Similar to memory from computer’s viewpoint • Output – Receive data from computer – Send data to peripheral • Input – Receive data from peripheral – Send data to computer 3 -44 Yonsei University

Input/Output Connection Interconnection structures • Receive control signals from computer • Send control signals to peripherals – e. g. spin disk • Receive addresses from computer – e. g. port number to identify peripheral • Send interrupt signals (control) 3 -45 Yonsei University

Interconnection structures CPU Connection • • 3 -46 Reads instruction and data Writes out data (after processing) Sends control signals to other units Receives (& acts on) interrupts Yonsei University

Interconnection Structure Interconnection structures • Interconnection structure support this type of transfers – Memory to processor: Processor reads instruction or unit of data from memory – Processor to memory: processor writes unit of data to memory – I/O to processor: processor reads data from I/O device via I/O module – Processor to I/O: Processor sends data to the I/O device – I/O to or from memory 3 -47 Yonsei University

Bus Interconnection Bus interconnection • Bus is communication pathway connecting two or more devices • Characteristic of bus is a shared transmission medium. • System bus connects major computer components (processor, memory, I/O) • There a number of possible interconnection systems • Single and multiple BUS structures are most common • e. g. Control/Address/Data bus (PC) • e. g. Unibus (DEC-PDP) 3 -48 Yonsei University

Bus interconnection What Is A Bus? • A communication pathway connecting two or more devices • Usually broadcast • Often grouped – A number of channels in one bus – e. g. 32 bit data bus is 32 separate single bit channels • Power lines may not be shown 3 -49 Yonsei University

Bus Structure – Data Bus interconnection • Data lines provide path for moving data between system module • Data lines collectively called “data bus” – Remember that there is no difference between “data” and “instruction” at this level • Width is a key determinant of performance – 8, 16, 32, 64 bit 3 -50 Yonsei University

Bus Structure - Address Bus interconnection • Address lines used to designate source or destination of the data on the data bus • e. g. CPU needs to read an instruction (data) from a given location in memory • Bus width determines maximum memory capacity of system – e. g. 8080 has 16 bit address bus giving 64 k address space 3 -51 Yonsei University

Bus Structure - Control Bus interconnection • Control lines used to control access to and use of data and address lines • Control and timing information – – – – – 3 -52 Memory write/read I/O write/read Transfer ACK Bus request Bus grant Interrupt request Interrupt ACK Clock Reset Yonsei University

Bus Interconnection Scheme 3 -53 Bus interconnection Yonsei University

Operation of Bus interconnection • One module wishes to send data to another – Obtain the use of the bus – Transfer data via the bus • One module wishes to request data from another module – Obtain the use of the bus – Transfer a request o the other module over the appropriate control and address lines – Wait for second module to send the data 3 -54 Yonsei University

Typical Physical Realization 3 -55 Bus interconnection Yonsei University

Big And Yellow? Bus interconnection • What do buses look like? – Parallel lines on circuit boards – Ribbon cables – Strip connectors on mother boards • e. g. PCI – Sets of wires 3 -56 Yonsei University

Single Bus Problems Bus interconnection • Lots of devices on one bus leads to: – Propagation delays • Long data paths mean that co-ordination of bus use can adversely affect performance • If aggregate data transfer approaches bus capacity • Most systems use multiple buses to overcome these problems 3 -57 Yonsei University

Multiple-Bus Hierarchies Bus interconnection • If a great number of devices connected to the bus, performance will suffer – More devices attached to the bus , the greater bus length and hence greater propagation delay – Bus become a bottleneck as the aggregate data transfer demand approaches capacity of bus 3 -58 Yonsei University

Bus interconnection Multiple-Bus Hierarchies • I/O devices attached to expansion bus • To build high-speed bus that closely integrated with the rest of system, requiring only a bridge between the processor’s bus and high speed bus 3 -59 Yonsei University

Traditional Bus Architecture 3 -60 Bus interconnection Yonsei University

High Performance Architecture Bus interconnection • The high speed bus brings high-demand devices into closer integration with the processor & independent of the processor at the same time • Difference in processor and high-speed bus speeds and signal line definition tolerated • Changes in processor architecture do not affect the high-speed bus, and vice versa 3 -61 Yonsei University

High Performance Architecture 3 -62 Bus interconnection Yonsei University

Elements of Bus Design Type Dedicated Multiplexed Method of Arbitration Centralized Distributed Timing Synchronous Asynchronous 3 -63 Bus interconnection Bus Width Address Data Transfer Type Read Write Read-modify-write Read-after-write Block Yonsei University

Bus Types Bus interconnection • Dedicated bus line – Functional dedication - Assign one function – Physical dedication - Refers to use of multiple bus & Connects subset of modules – Advantage – High through-put – Disadvantage – Increased size and cost of the system • Multiplexed – – 3 -64 Shared lines Address valid or data valid control line Advantage - Fewer lines Disadvantages - More complex control & Ultimate performance Yonsei University

Method of Arbitration Bus interconnection • Method of arbitration needed because only one unit successfully transmit over the bus at a time • Bus Arbitration – – More than one module controlling the bus e. g. CPU and DMA controller Only one module may control bus at one time Arbitration may be centralised or distributed • Centralised Arbitration – Single hardware device controlling bus access • Bus Controller • Arbiter – May be part of CPU or separate • Distributed Arbitration – Each module may claim the bus – Control logic on all modules 3 -65 Yonsei University

Timing Bus interconnection • Co-ordination of events on bus • The bus includes a clock line upon which clock transmits a regular sequence of alternating 1 s & 0 s of equal duration • A single 1 -0 transmission referred to as a clock cycle of bus cycle 3 -66 Yonsei University

Synchronous Timing Bus interconnection • • Events determined by clock signals Control Bus includes clock line A single 1 -0 is a bus cycle All devices can read clock line Usually bus signal change on leading edge Usually a single cycle for an event Synchronous timing simpler to implement and test • Less flexible than asynchronous timing 3 -67 Yonsei University

Synchronous Timing 3 -68 Bus interconnection Yonsei University

Asynchronous. Timing Bus interconnection • Occurrence of event depends on occurrence of previous event • Mixture of slow and fast device • Using older and newer technology • Can share bus 3 -69 Yonsei University

Asynchronous Timing 3 -70 Bus interconnection Yonsei University

Bus Data Transfer Types 3 -71 Bus interconnection Yonsei University

PCI • Peripheral Component Interconnection • Popular high-bandwidth, processor-independent bus that function as mezzanine or peripheral bus • Delivers better system performance for high-speed I/O subsystems 3 -72 Yonsei University

Example PCI Configurations 3 -73 PCI Yonsei University

Example PCI Configurations 3 -74 PCI Yonsei University

Interpretation of PCI Read Commands Read Command Type For Cachable Memory PCI For Noncachable Memory Read Bursting one-half or less of a cache line Bursting 2 data transfer cycles of less Memory Read Line Bursting more than one-half a cache line to three cache lines Bursting 3 to 12 data transfers Memory Read Multiple Bursting more than three cache lines Bursting more than 12 data transfers 3 -75 Yonsei University

PCI Bus Lines - Required PCI • Systems Lines – Including clock and reset • Address & Data – 32 time mux lines for address/data – Interrupt & validate lines • Interface Control • Arbitration – Not shared – Direct connection to PCI bus arbiter • Error Lines 3 -76 Yonsei University

PCI Bus Lines - Optional PCI • Interrupt lines – Not shared • Cache support • 64 -bit Bus Extension – Additional 32 lines – Time multiplexed – 2 lines to enable devices to agree to use 64 -bit transfer • JTAG/Boundary Scan – For testing procedures 3 -77 Yonsei University

PCI Commands PCI • The commands are – – – 3 -78 Interrupt Acknowledge Special Cycle I/O Read I/O Write Memory Read line Memory Read Multiple Memory Write and Invalidate Configuration Read Configuration Write Dual Address Cycle Yonsei University

PCI Commands PCI • Interrupt Acknowledge is a read command intended for device that function as interrupt controller on the PCI bus • The Special Cycle command used by initiator to broadcast message to one or more targets • I/O Read and Write commands used to transfer data between initiator and I/O controller • Memory Write command used to transfer data one or more data cycles to memory 3 -79 Yonsei University

PCI Commands PCI • Memory Write & Invalidate command transfers data in one or more cycles to memory • Two configuration commands enable master to read and update configuration parameters in device connected to PCI • Dual Address Cycle command used by initiator to indicate that using 64 -bit addressing 3 -80 Yonsei University

PCI Read Operation 3 -81 PCI Yonsei University

Arbitration PCI • PCI use of centralized, synchronous arbitration scheme • Each master has unique request(REQ), grant(GNT) signal • Simple request-grant handshake used to grant access to bus • Arbitration can take place at the same time that current bus master performing data transfer • Hidden arbitration – No bus cycles lost in performing arbitration 3 -82 Yonsei University

PCI Bus Arbiter 3 -83 PCI Yonsei University

PCI Bus Arbitration Between Two Master 3 -84 Yonsei University PCI