Chapter 3 Memory Basics Memory n A major

Chapter 3 Memory Basics

Memory ? ? ? n A major component of a digital computer and many digital systems. n Stores binary data, either permanently or temporarily. n Consists of arrays of elements: latches, capacitors or MOS transistors.

Overview n n n n Memory definitions Random Access Memory (RAM) Static RAM (SRAM) integrated circuits q Cells and slices q Cell arrays and coincident selection Arrays of SRAM integrated circuits Dynamic RAM (DRAM) integrated circuits DRAM Types q Synchronous (SDRAM) q Double-Data Rate (DDR SRAM) q RAMBUS DRAM (RDRAM) Arrays of DRAM integrated circuits

Memory Definitions n n Collection of cells capable of storing binary information. Contains electronic circuits for storing & retrieving information. Used to provide temporary or permanent storage capability. Semiconductor memories consists of arrays of elements that are generally latches, capacitors or MOS transistors.

A 64 -cell memory array organized in 3 different ways Thomas L. Floyd Digital

Memory Address and Capacity Each memory location needs an address. If the memory is addressed to a cell, then one bit is addressed. But, if the memory is addressed to the Byte or Word than that is the smallest amount of data that can be addressed.

Examples of memory address Bit/Cell Addressing Byte/Word/ Row Addressing Thomas L. Floyd Digital Fundamentals, 8 e Copyright © 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Example of memory address in 3 -D array

Memory Units n n Bit : a single binary digit. Nibble : a group of 4 bits accessed together. n Byte : a group of 8 bits accessed together. n Word : a group of binary bits whose size is a typical unit of access for the memory. (e. g. , 1 byte, 2 bytes, 4 bytes, 8 bytes, etc. )

Memory data elements n Memory Data q n A bit or a group of bits to be stored into or accessed from memory cells. Memory Operations q Operations on memory data supported by the memory unit. Typically, read and write operations over some data element (bit, byte, word, etc. ).

Basic Memory Operations n Write operation q n Puts data into a specified address in memory. Read Operation q Takes data out of a specified address in memory.

Block Diagram of a Memory Unit Bidirectional

3 -D Memory Array Note the separate Row and Column address decoders…

The ‘Write’ operation

The ‘Read’ operation

Types of Memories n Random Access Memory (RAM) q q n Write operation – stores new info. Read operation – transfer the stored info out of memory. Read Only Memory (ROM) q Performs the Read operation only ?

RAMs n RAM – (Random-access memory) n Data can be written into or read from any selected address in any sequence. q q When writing, original data in the cell address is replaced with new data. When reading, the cell data remains there. n RAM lose of stored data when power is turned off – volatile memories. n Usually used for short-term data storage.

ROMs n n ROM – (Read-only memory) Data is stored permanently or semipermanently. Data is read but a write operation as in a RAM memory is also possible with special equipment. Still random access like RAM, but ROMs retain data even when power is turned off.

Memory Basic Process n n n Info/content from memory is sent to h/w (usually consists of registers & combinational logic) to be processed. The processed info is then returned to the same or different memory address. Input and Output devices may also interact with memory. Printers Mouse Keyboard Monitor Digital Camera Scanners Plotters Thumb Drive External Memory I/O Memory Hardware for processing

Calculator Exercise n 2 8 = n 2 12 = n 2 16 = n 2 24 = n 2 32 = 256 4, 096 65, 536 16, 777, 216 4, 294, 967, 296

Memory Organization n Organized as an indexed array of words. Value of the index for each word is the memory address. n Often organized to fit the needs of a particular computer architecture. Some historically significant computer architectures and their associated memory organization: q Digital Equipment Corporation PDP-8 (DEC Alpha) n q used a 12 -bit address to address 4096 12 -bit words. IBM 360 used a 24 -bit address to address 16, 777, 216 8 -bit words, or 4, 194, 304 32 -bit words. n q Intel 8080 (8 -bit predecessor to the 8086 and the current Intel processors) n used a 16 -bit address to address 65, 536 8 -bit (bytes).

Address bus width vs No. of Memory words Address bus width No. of memory words 12 bits 4, 096 bits 16 bits 65, 536 bits 24 bits 16, 777, 216

Memory Block Diagram A basic memory system is shown here: Ø k address lines are decoded to address 2 k words of memory. Ø Each word is n bits. Ø Read and Write are single control lines defining the simplest of memory operations. (Refer to next slide for example)

Memory Organization Example of memory contents above: • No. of data bits = 8; n = 8 • No. of address bits = 3; k = 3 • Therefore the number of address lines = m = (2 k); 23 = 8 • Address range: 0 to 2 k -1; therefore 0 to 23 – 1, Add. Range: 0 to 7 • 1 word is the size of the memory content; so the memory above has 8 words of 8 -bit data

The ‘Write’ operation k=3 No. of columns = No. of Data bits n = No. of Data input & ouput lines n=8 No. of add. Rows (locations) m = 2 k = 8 n-bits per word

Memory Size No. of words x Data width No. of address lines No. of bits per word

Memory Size Units q K (Kilo) = 210 q M (Mega) = 220 q G (Giga) = 230 Examples : q 64 K = 216 = (26 * 210) q 2 M = 221 = (21 * 220) q 4 G = 232 = (22 * 230)

Memory Organization Example • Address bits = k = 10. • Address lines = (2 k) 210 = 1024 or 1 K, labeled 0 to 1023. • Data bits =16; n = 16. • Memory content = 16 bit. • Memory Capacity is 1 K words of 16 -bits each, or “ 1 K x 16 bits”.

Memory Operations n Memory operations require the following: q q q n Read Memory ─ an operation that reads a data value stored in memory: (takes from memory) q q q n Place a valid address on the address lines Activate the Read input. Note : the content of the selected word are not changed by reading them Write Memory ─ an operation that writes a data value to memory: q q q n Data Address An operation ─ Typical operations are READ and WRITE. (RAM) Place a valid address on the address lines Apply data on the data lines Activate the Write input Other than Read/Write (R/W) Chip Select is used to enable a particular RAM. It is sometimes called Memory Enable.

Memory Enable

Exercise Questions 1. How many address lines and data lines are needed for each of the following memories? n 16 K x 8 n 256 K x 16 n 64 M x 32 n 2 G x 8

… Exercise Questions 2. Sketch the memory organisation for each of the following memories. n 16 K x 8 n 256 K x 16 n 64 M x 32 n 2 G x 8

… Exercise Questions 3. Give the no. of bytes stored in each of the following memories. n 16 K x 8 n 256 K x 16 n 64 M x 32 n 2 G x 8

ROM Read Only Memory

The ROM family Thomas L. Floyd Digital Fundamentals, 9 e Copyright © 2006 by

ROM cells Thomas L. Floyd Digital Fundamentals, 9 e Copyright © 2006 by Pearson

A representation of a 16 x 8 -bit ROM array Thomas L. Floyd Digital

MOS PROM array with fusible links Thomas L. Floyd Digital Fundamentals, 9 e Copyright

Ultraviolet erasable PROM (EPROM) package Thomas L. Floyd Digital Fundamentals, 9 e Copyright ©

The storage cell in a flash memory Uses “Foating Gate” MOS transistor Example Application: MEMORY STICKs Thomas L. Floyd Digital Fundamentals, 9 e Copyright © 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

RAM Random Access Memory

RAM Integrated Circuit n Types of random access memory (RAM) q q Static – information stored in latches Dynamic – information stored as electrical charges on capacitors n n n Charge “leaks” off Periodic “refresh” of charge required Dependence on Power Supply Volatile – loses stored information when power is turned off (example : FPGA – Flex 10 K). Both static and dynamic RAM are volatile. Non-volatile – retains information when power is turned off.

The RAM family

SRAM ICs SRAM = Static RAM

Static RAM �Cell n Array of storage cells used to implement static RAM Select n Storage Cell q q SR Latch Select input for control Dual Rail Data Inputs B and B Dual Rail Data Outputs C and C B B S Q R Q C C RAM cell

Static RAM �Bit Slice n Represents all circuitry that is required for 2 n 1 -bit words Word select 0 q q Multiple RAM cells Control Lines: n n n q Select B B Word select i – one for each word Bit Select n Data in Data out Q R Q XC C X RAM cell Word select 0 RAM cell Word select 1 Word select 2 n � 1 Data Lines: n S RAM cell Select S Q R Q Word select 2 n � 1 X RAM cell Read/Write logic Data in S Q R Q Data in Data out Read/ Bit Write select (b) Symbol n here is previously mentioned as “k” Write logic Read/ Write Read logic Bit select (a) Logic diagram Data out

n 2 -Word n 1 -Bit RAM IC To build a RAM IC from a RAM slice, we need: q Decoder � decodes the n address lines to 2 n word select lines q A 3 -state buffer � n on the data output permits RAM ICs to be combined into a RAM with c 2 n words A 3 A 2 A 1 A 0 16 x 1 RAM A 0 Data output Data input Read/ Write Word select 4 -to-16 Decoder 0 1 23 2 RAM cell 3 22 4 5 21 6 RAM cell 0 7 2 8 9 10 11 12 13 14 15 RAM cell Memory enable Read/Write logic (a) Symbol Data input Data in Data out Read/ Bit Write select Read/Write n here is previously mentioned as “k” Chip select (b) Block diagram Data output

RAM : Cell Arrays and Coincident Selection n Memory arrays can be very large => q q q Large decoders Large fanouts for the bit lines However, the decoder size and fanouts (outputs) can be reduced by using a coincident selection in a 2 -dimensional array: n Uses two decoders, one for words and one for bits q q Word select becomes Row select Bit select becomes Column select

Coincident… ? ?

Previous 16 x 1 RAM

Coincident Selection Approach for the 16 X 1 RAM Chip • 4 bit address [A 3. . A 0] thus 24 = 16 RAM cells • The column decoder is enabled with the CS input • When CS =0, column decoder is disabled and all o/p’s are 0 and NONE of the cells are selected n A 3 and A 2 used for Row select n A 1 and A 0 for Column select 16 X 1 RAM using 4 X 4 RAM Cell Array

Coincident Selection Approach If Address is 1001: • A 3, A 2 = 10, row decoder line 2 active • Activating RAM 8, 9, 10 & 11 • A 1, A 0 = 01, column decoder line 1 active • Activating RAM 1, 5, 9, 13 • The intersect RAM, RAM 9, is activated. Other RAM cells not selected are disabled. • Then it depends on the operation functions (Read or Write) • Read : Data out thru OR gate and tri-state buffer • Write : Data available on the Data input line is transferred into the 4 x 4 RAM Cell Array selected RAM cell.

Constructing RAM n Previously : Block Diagram of a 16 X 1 RAM using 4 X 4 RAM Cell Array. n How to create 8 X 2 RAM using 4 X 4 RAM Cell Array? q q Number of Address bits = 3 -bits (8 = 23) Number of Data bits = 2 -bits

cau. Tio. N … do No. T ge. T con. Fu. Sed… MEMORY SIZE ARRAY SIZE n 16 K x 8 n 16 X 1 n 256 K x 16 n 4 X 4 n 64 M x 32 n 8 X 2 n 2 G x 8 VERSUS

3 -bits addressing • 2 -bits at Row Decoder • 1 -bit at Column Decoder Since 2 bits at a time are to be written or read: 2 input lines • Data input 0 • Data input 1 2 output lines • Data output 0 • Data output 1 Example: If Address is = 011 Row Decoder = line 1 RAM = 4, 5, 6 & 7 Column Decoder = line 1 RAM = 2, 6, 10, 14 and 3, 7, 11, 15 Therefore : Cells 6 & 7 are activated Construct 8 x 2 RAM using 4 x 4 RAM cell array

Constructing other RAM sizes… n How about the 32 K X 8 bit? n No. Address bits = 15 -bits No. Data bits = 8 n n n (32 x 210 = 25 x 210) Without Coincident selection a single decoder would have 15 inputs and 32, 768 outputs. (32 x 1 K = 32 x 1024) And 32, 800 no of gates.

… Constructing RAM n With Coincident selection: q q q Make row and column equal Total no. of RAM cells = 32 K x 8 = 256 K = 262, 144 Take Square Root of 262144 = 512 n q q q (No. columns = No. Rows) 512 = 29 , meaning 9 -bits is fed to the ROW Decoder. Remaining 6 -bits is fed to the COLUMN Decoder. Row Decoder : 9 to 512 line decoder Column Decoder : 6 to 64 line decoder No of gates = 608

Memory Expansion Increase word length, or word capacity, or both

Word-Length Expansion n Word Length = No. of bits per word n To increase the word length, the no. of bits in the data bus must be increased.

Example of Word-Length Expansion n Use this 64 K x 4 RAM cell to build: 1. 64 K x 8 RAM 2. 64 K x 16 RAM

Solution: The 64 K x 8 Thomas L. Floyd Digital Fundamentals, 9 e Copyright

Solution: The 64 K x 16 Thomas L. Floyd Digital Fundamentals, 9 e Copyright

Illustration of word-length expansion with two 2 m x n RAMs forming a 2 m x 2 n RAM Thomas L. Floyd Digital Fundamentals, 9 e Copyright © 2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

In Detailed Block Diagram form

The 64 K x 4 RAM Thomas L. Floyd Digital Fundamentals, 9 e Copyright

The 64 K x 8 RAM Thomas L. Floyd Digital Fundamentals, 9 e Copyright

Word-Capacity Expansion n Word Capacity = No. of words n To increase the word capacity, the no. of address locations is increased. n To achieve this, the no. of address bits must be increased.

Word Capacity Expansion Example Thomas L. Floyd Digital Fundamentals, 9 e Copyright © 2006

In block diagram form Thomas L. Floyd Digital Fundamentals, 9 e Copyright © 2006

Conclude… n 1 M x 8 q n 220 20 -bits of address lines 2 M x 8 q 2 x 220 = 221 21 -bits of address lines n Adding 1 -bit to the address line results in doubling the no. of words

Expansion of Memory u. Sin. G Array of SRAM ICs … ? - Making Larger or Wider from Smaller Ones… Memories

ARRAY of SRAM ICs n n n If an application is larger than the capacity of one chip, then There is a need to combine a number of chips in an array to form a required size of memory. Depends on 2 parameters q q n No. of address lines No. of words q n No. of words No. of bits per word 1 -bit added to the address would double the no. of words No. of bits per word No. of data input & output lines q If 1 -bit is added to the word size, 1 data input & output line must be added

Bigger. . h. OW ? n n To make wider memories (bigger memory data size) No. of bits per word No. of data input & output lines q If 1 -bit is added to the word size, 1 data input & output line must be added To make larger memories (more address locations) No. of address lines No. of words q 1 -bit added to the address would double the no. of words

Make wider memories …

What if we were to expand the word size? n Example : 64 K X 16 using 64 K X 8 chips. No. of chips to be used refers to the word size. In this case, 16 -bits is to be constructed from 8 -bit words. Therefore 2 of 64 K X 8 Chip is to be used. n Connections: n n n q q Address line is input to both chips CS is common to both chips R/W control input is also common to both chips INPUT & OUTPUT DATA LINE is SPLIT

Making Wider Memories n n n To construct wider memories from narrow ones, we tie the address and control lines in parallel and keep the data lines separate. For example, to make a 4 word by 4 -bit memory from 4, 4 -word by 1 -bit memories Note: Both 16 x 1 and 4 x 4 memories take 4 -chips and hold 16 bits of data. Construct 4 x 4 using 4 x 1

Constructing a 64 K X 16 using 64 K X 8 chip Din [15. . 8] Din [7. . 0] Dout [15. . 8] Dout [7. . 0]

Make Larger memories …

Making Larger Memories n n Using the CS lines, we can make larger memories from smaller ones by tying all address, data, and R/W lines in parallel, and using the decoded higher order address bits to control CS. Using the 4 -Word by 1 Bit memory from before, we construct a 16 -Word by 1 -Bit memory. Construct 16 x 1 using 4 x 1

Lets say u have this memory Chip. • How to construct a 256 K X 8 RAM using this 64 K X 8 RAM Chip? • No. of words is the same (8 -bits) • No. of address lines are not the same (64 K 256 K) • 64 K 16 -bit address (26 x 210) • 256 18 -bit address (28 x 210) • An additional 2 -bits is needed for the address bit

Constructing 256 K X 8 RAM using 64 K x 8 RAM Chip n n 2 additional address bits are applied to a 2 x 4 decoder and represent the MSB of the address bit. How many 64 K x 8 RAM chip to add? Additional 2 -bits 22 = 4 of 64 x 8 RAM Use Memory Enable to activate the decoder.

Constructing 256 K X 8 RAM using 64 K x 8 RAM Chip When bit 17 and 16 = 00 The first 64 x 8 RAM is activated Address : 0 – 65, 535 When bit 17 and 16 = 01 The 2 nd 64 x 8 RAM is activated Address : 65, 536 – 131, 071 When bit 17 and 16 = 10 The 3 rd 64 x 8 RAM is activated Address : 131, 071 – 196, 607 When bit 17 and 16 = 11 The 4 th 64 x 8 RAM is activated Address : 196, 608 – 262, 143 Construct 256 Kx 8 using 64 Kx 8

Conclude… n n Add 2 more extra bits to the address input and get ? 4 ____ times more no. of words (address locations). q From 64 K to 256 K

Exercise To be handed in …

Construct these SRAM memory chips n A 512 K x 8 using 32 K x 8. n A 128 K x 16 using 128 K x 4. n A 512 K x 16 using 64 K x 8 n A 1024 K x 16 using 32 K x 8.

Dynamic RAM (DRAM)

Dynamic RAM (DRAM) n n n Basic Principle: Storage of information on capacitors. Charge and discharge of capacitor to change stored value Use of transistor as “switch” to: q q n Store charge Charge or discharge See next slide for circuit, hydraulic analogy, and logical model.

DRAM ICs n n Provide high storage capacity at low cost, it dominates the high-capacity memory applications, e. g : Primary RAM in computers DRAM in many ways similar to SRAM except it must be periodically “refreshed”

DRAM Cell n It consist of Capacitor C and Transistor T. q q q n Capacitor store electric charge Sufficient charge = logic 1 Insufficient charge = logic 0 Transistor T q q q Act as a switch Switch open = the charge on capacitor remains fixed (stored) Switch closed = charge flow in and out, this allows the cell to be READ or WRITE

Dynamic RAM (continued) Select T B Stored 0 Stored 1 To Pump C DRAM cell (b) (a) (c) Write 1 Write 0 Select B D Q C C (d) (e) Read 1 Read 0 DRAM cell model (h) (f) (g)

Dynamic RAM - Bit Slice n n n C is driven by 3 -state drivers Sense amplifier is used to change the small voltage change on C into H or L In the electronics, B, C, and the sense amplifier output are connected to make destructive read into non-destructive read Word select 0 Select B D C Q C Word select 0 DRAM cell model DRAM cell Word select 1 Word select 2 n 2 1 DRAM cell Select D Word select 2 n 2 1 Q C DRAM cell model DRAM cell Read/Write logic Sense amplifier Data in Data out Read/ Bit Write select (b) Symbol Write logic Read/ Write Bit select (a) Logic diagram Read logic Data out

Hydraulic Analogy for DRAM Cell (b) Small tank full = storing logic 1 (c) Small tank empty = storing logic 0 In this state the valve is closed

Hydraulic Analogy for DRAM Cell (d) To write a logic 1: • Pump will fill up big tank • Valve open • Water flows from big tank to small tank • Once small tank is full, the valve is closed (e) To write a logic 0: • Pump will empty big tank • Valve open • Water flows from small tank to big tank • Once small tank is emptied (almost emptied), the valve is closed

Hydraulic Analogy for DRAM Cell Note : Once the water level in storage increase or decrease in the READ operation, the level left in storage will not showing the actual value of the storage anymore. This is called Destructive Read To store the original value, we must perform a restore operation to the storage (to return the small tank to its original level)

Hydraulic Analogy for DRAM Cell (f) Reading 1 from storage (small tank) • Large tank at known intermediate level • Valve opened • IF Water flow from small tank to large tank • Water increase slightly in large tank • This slight increase depict READ value of logic 1 from storage (g) Reading 0 from storage (small tank) • Large tank at known intermediate level • Valve opened • IF Water flow from large tank to small tank • Water decrease slightly in large tank • This slight decrease depict READ value of logic 0 from storage

Logic Model of DRAM Dynamic RAM cell circuit Logic Model of DRAM • In actual, there is another consideration for dynamic RAM. • The analogous leakage (due to the use of capacitors) • Due to this leaks, a full storage tank will eventually drain to a point which an increase in the level of the large tank on a READ operation cannot be observed. • To compensate, a refresh is needed.

DRAM : Block Diagram

DRAM : Block Diagram n The addressing is applied serially in two parts: q Row address q Column address n In order to hold the row address throughout the READ or WRITE operation, it is stored in a register. n Signal that control the loading of the registers are: q RAS : Row Address Strobe q CASS : Column Address Strobe q R/W : Read / Write q OE : Output Enable Note : the LOW signals activate Read, Write and Output enable. This is because when Write operation is activated, there should not be any Data output.

DRAM : Block Diagram n n n The refresh counter and refresh controller is used to control the refresh rate for the DRAM. Typical refresh rate is between 16 to 64 milliseconds 2 types of refresh: q q Distributed refresh (more commonly used) Burst refresh

DRAM Types n n n FPM DRAM (Fast Page Mode DRAM) EDO DRAM (Extended Data Output DRAM) SDRAM (Synchronous DRAM) DDR SDRAM (Double Data Rate SDRAM) RDRAM (Rambus® DRAM) ECC (Error Correcting Code)

DRAM Types n n Types to be discussed q Synchronous DRAM (SDRAM) q Double Data Rate SDRAM (DDR SDRAM) q RAMBUS® DRAM (RDRAM) Justification for effectiveness of these types q DRAM often used as a part of a memory hierarchy (See details in chapter 14) q Reads from DRAM bring data into lower levels of the hierarchy q Transfers from DRAM involve multiple consecutively addressed words q Many words are internally read within the DRAM ICs using a single row address and captured within the memory q This read involves a fairly long delay

DRAM Types (continued) n n Justification for effectiveness of these types (continued) q These words are then transferred out over the memory data bus using a series of clocked transfers q These transfers have a low delay, so several can be done in a short time q The column address is captured and used by a synchronous counter within the DRAM to provide consecutive column addresses for the transfers burst read – the resulting multiple word read from consecutive addresses

Synchronous DRAM n n Transfers to and from the DRAM are synchronize with a clock Synchronous registers appear on: q q q n Column address counter q q n Address input Data output for addressing internal data to be transferred on each clock cycle beginning with the column address counts up to column address + burst size – 1 Example: Memory data path width: 1 word = 4 bytes Burst size: 8 words = 32 bytes Memory clock frequency: 5 ns Latency time (from application of row address until first word available): 4 clock cycles Read cycle time: (4 + 8) x 5 ns = 60 ns Memory Bandwidth: 32/(60 x 10 -9) = 533 Mbytes/sec

Double Data Rate Synchronous DRAM n n n Transfers data on both edges of the clock Provides a transfer rate of 2 data words per clock cycle Example: Same as for synchronous DRAM q q Read cycle time = 60 ns Memory Bandwidth: (2 x 32)/(60 x 10 -9) = 1. 066 Mbytes/sec

RAMBUS DRAM (RDRAM) n n Uses a packet-based bus for interaction between the RDRAM ICs and the memory bus to the processor The bus consists of: q q q n n The bus is synchronous and transfers on both edges of the clock Packets are 4 -clock cycles long giving 8 transfers per packet representing: q q q n n A 3 -bit row address bus A 5 -bit column address bus A 16 or 18 -bit (for error correction) data bus A 12 -bit row address packet A 20 -bit column address packet A 128 or 144 -bit data packet Multiple memory banks are used to permit concurrent memory accesses with different row addresses The electronic design is sophisticated permitting very fast clock speeds

Arrays of DRAM Integrated Circuits n Similar to arrays of SRAM ICs, but there are differences typically handled by an IC called a DRAM controller: q q Separation of the address into row address and column address and timing their application Providing RAS and CAS and timing their application Performing refresh operations at required intervals Providing status signals to the rest of the system (e. g. , indicating whether or not the memory is active or is busy performing refresh)

Table 9. 2 : Morris Mano, pg 422

Assigment Folder Questions Chapter 9 n 1, 2, 3, 4, 5, 9, 10, [12]

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