Chapter 3 Instruction Level Parallelism Dr Eng Amr

Chapter 3 Instruction Level Parallelism Dr. Eng. Amr T. Abdel-Hamid Spring 2011 Text book slides: Computer Architecture: A Quantitative Approach 4 th Edition, John L. Hennessy & David A. Patterso Computer Applications Elect 707

Recall from Pipelining Review Pipelined CPI = Ideal pipeline CPI + Structural Stalls + Data Hazard Stalls + Control Stalls Dr. Amr Talaat Ø Ideal pipeline CPI: measure of the maximum performance attainable by the implementation Ø Structural hazards: HW cannot support this combination of instructions Ø Data hazards: Instruction depends on result of prior instruction still in the pipeline Ø Control hazards: Caused by delay between the fetching of instructions and decisions about changes in control flow (branches and jumps) Elect 707

Reduction of Pipeline Hazards Techniques Today Dr. Amr Talaat Elect 707

Instruction Level Parallelism Ø Instruction-Level Parallelism (ILP): overlap the execution of instructions to improve performance. Ø 2 main approaches to exploit ILP: 1) Rely on hardware to help discover and exploit the parallelism dynamically (e. g. , Pentium 4) 2) Rely on software technology to find parallelism, statically at compile-time (e. g. , Itanium 2) Dr. Amr Talaat Elect 707

Floating-Point Pipeline Dr. Amr Talaat Elect 707

Dynamic Scheduling Ø Dynamic scheduling: hardware rearranges the instruction execution to reduce stalls while maintaining data flow and exception behavior Ø It handles cases when dependences unknown at compile time Ø it allows the processor to tolerate unpredictable delays such as cache misses, by executing other code while waiting for the miss to resolve Ø It allows code that compiled for one pipeline to run efficiently on a different pipeline Ø It simplifies the compiler Dr. Amr Talaat Elect 707

HW Schemes: Instruction Parallelism Ø Key idea: Allow instructions behind stall to proceed DIVD ADDD SUBD F 0, F 2, F 4 F 10, F 8 F 12, F 8, F 14 Ø Enables out-of-order execution and allows out-of-order completion (e. g. , SUBD) Ø In a dynamically scheduled pipeline, all instructions still pass through issue stage in order (in-order issue) Dr. Amr Talaat Ø Will distinguish when an instruction begins execution and when it completes execution; between 2 times, the instruction is in execution Ø Note: Dynamic execution creates WAR and WAW hazards Elect 707

Dynamic Scheduling Step 1 Ø Simple pipeline had 1 stage to check both structural and data hazards: Instruction Decode (ID), also called Instruction Issue Ø Split the ID pipe stage of simple 5 -stage pipeline into 2 stages: Ø Issue—Decode instructions, check for structural hazards Ø Read operands—Wait until no data hazards, then read operands Dr. Amr Talaat Elect 707

A Dynamic Algorithm: Tomasulo’s Ø For IBM 360/91 (before caches!) Ø Long memory latency Ø Goal: High Performance without special compilers Ø Small number of floating point registers (4 in 360) prevented interesting compiler scheduling of operations Ø This led Tomasulo to try to figure out how to get more effective registers — renaming in hardware! Ø Why Study 1966 Computer? Ø The descendants of this are used in: Dr. Amr Talaat Ø Alpha 21264, Pentium 4, AMD Opteron, Power 5, … Elect 707

Tomasulo Organization FP Registers From Mem FP Op Queue Load Buffers Load 1 Load 2 Load 3 Load 4 Load 5 Load 6 Store Buffers Add 1 Add 2 Add 3 Mult 1 Mult 2 Dr. Amr Talaat FP adders Elect 707 Reservation Stations To Mem FP multipliers

Reservation Station Components Op: Operation to perform in the unit (e. g. , + or –) Vj, Vk: Value of Source operands Qj, Qk: Reservation stations producing source registers (value to be written) Ø Note: Qj, Qk=0 => ready Ø Store buffers only have Qi for RS producing result Busy: Indicates reservation station or FU is busy Dr. Amr Talaat Register result status—Indicates which functional unit will write each register, if one exists. Blank when no pending instructions that will write that register. Elect 707

Three Stages of Tomasulo Algorithm 1. Issue—get instruction from FP Op Queue If reservation station free (no structural hazard), control issues instr & sends operands (renames registers). 2. Execute—operate on operands (EX) When both operands ready then execute; if not ready, watch Common Data Bus for result 3. Write result—finish execution (WB) Write on Common Data Bus to all awaiting units; mark reservation station available Ø Normal data bus: data + destination (“go to” bus) Ø Common data bus: data + source Dr. Amr Talaat Ø Example speed: 3 clocks for Fl. pt. +, -; 10 for * ; 40 clks for / Elect 707

Tomasulo Example Instruction stream 3 Load/Buffers FU count down Dr. Amr Talaat Clock cycle counter Elect 707 3 FP Adder R. S. 2 FP Mult R. S.

Tomasulo Example Cycle 1 Dr. Amr Talaat Elect 707

Tomasulo Example Cycle 2 Dr. Amr Talaat Note: Can have multiple loads outstanding Elect 707

Tomasulo Example Cycle 3 • Note: registers names are removed (“renamed”) in Reservation Stations; MULT issued • Load 1 completing; what is waiting for Load 1? Dr. Amr Talaat Elect 707

Tomasulo Example Cycle 4 Dr. Amr Talaat • Load 2 completing; what is waiting for Load 2? Elect 707

Tomasulo Example Cycle 5 Dr. Amr Talaat • Timer starts down for Add 1, Mult 1 Elect 707

Tomasulo Example Cycle 6 Dr. Amr Talaat • Issue ADDD here despite name dependency on F 6? Elect 707

Tomasulo Example Cycle 7 Dr. Amr Talaat • Add 1 (SUBD) completing; what is waiting for it? Elect 707

Tomasulo Example Cycle 8 Dr. Amr Talaat Elect 707

Tomasulo Example Cycle 9 Dr. Amr Talaat Elect 707

Tomasulo Example Cycle 10 Dr. Amr Talaat • Add 2 (ADDD) completing; what is waiting for it? Elect 707

Tomasulo Example Cycle 11 • Write result of ADDD here? • All quick instructions complete in this cycle! Dr. Amr Talaat Elect 707

Tomasulo Example Cycle 12 Dr. Amr Talaat Elect 707

Tomasulo Example Cycle 13 Dr. Amr Talaat Elect 707

Tomasulo Example Cycle 14 Dr. Amr Talaat Elect 707

Tomasulo Example Cycle 15 Dr. Amr Talaat • Mult 1 (MULTD) completing; what is waiting for it? Elect 707

Tomasulo Example Cycle 16 Dr. Amr Talaat • Just waiting for Mult 2 (DIVD) to complete Elect 707

(skip a couple of cycles) Dr. Amr Talaat Elect 707

Tomasulo Example Cycle 55 Dr. Amr Talaat Elect 707

Tomasulo Example Cycle 56 Dr. Amr Talaat • Mult 2 (DIVD) is completing; what is waiting for it? Elect 707

Tomasulo Example Cycle 57 Dr. Amr Talaat • Once again: In-order issue, out-of-order execution and out-oforder completion. Elect 707

Why can Tomasulo overlap iterations of loops? Ø Register renaming Ø Multiple iterations use different physical destinations for registers (dynamic loop unrolling). Ø Reservation stations Ø Permit instruction issue to advance past integer control flow operations Ø Also buffer old values of registers - totally avoiding the WAR stall Ø Other perspective: Tomasulo building data flow dependency graph on the fly Dr. Amr Talaat Elect 707

Tomasulo Loop Example Loop: LD MULTD SD SUBI BNEZ F 0 F 4 R 1 Ø Multiply takes 4 clocks Ø Load have cache misses Dr. Amr Talaat Elect 707 0 F 0 0 R 1 Loop R 1 F 2 R 1 #8

Loop Example Cycle 0 Dr. Amr Talaat Elect 707

Loop Example Cycle 1 Dr. Amr Talaat Elect 707

Loop Example Cycle 2 Dr. Amr Talaat Elect 707 3 8

Loop Example Cycle 3 Dr. Amr Talaat Elect 707 3 9

Loop Example Cycle 4 Dr. Amr Talaat Elect 707 4 0

Loop Example Cycle 5 Dr. Amr Talaat Elect 707 4 1

Loop Example Cycle 6 Dr. Amr Talaat Elect 707

Loop Example Cycle 7 Dr. Amr Talaat Elect 707 4 3

Loop Example Cycle 8 Dr. Amr Talaat Elect 707 4 4

Loop Example Cycle 9 Dr. Amr Talaat Elect 707 4 5

Loop Example Cycle 10 Dr. Amr Talaat Elect 707 4 6

Loop Example Cycle 11 Dr. Amr Talaat Elect 707 4 7

Loop Example Cycle 12 Structural hazard – no MULT unit available Dr. Amr Talaat Elect 707 4 8

Loop Example Cycle 13 Dr. Amr Talaat Elect 707 4 9

Loop Example Cycle 14 Dr. Amr Talaat Elect 707 5 0

Loop Example Cycle 15 Dr. Amr Talaat Elect 707 5 1

Loop Example Cycle 16 Dr. Amr Talaat Elect 707 5 2

Loop Example Cycle 17 Dr. Amr Talaat Elect 707 5 3

Loop Example Cycle 18 Dr. Amr Talaat Elect 707 5 4

Loop Example Cycle 19 Dr. Amr Talaat … Elect 707 5 5

Loop Example Cycle 20 Dr. Amr Talaat Elect 707 5 6

Loop Example Cycle 21 Dr. Amr Talaat Elect 707 5 7

Tomasulo’s scheme offers 2 major advantages 1. Distribution of the hazard detection logic Ø distributed reservation stations and the CDB Ø If multiple instructions waiting on single result, & each instruction has other operand, then instructions can be released simultaneously by broadcast on CDB Ø If a centralized register file were used, the units would have to read their results from the registers when register buses are available 2. Elimination of stalls for WAW and WAR hazards Dr. Amr Talaat Elect 707

Tomasulo Drawbacks Ø Complexity Ø Many associative stores (CDB) at high speed Ø Performance limited by Common Data Bus Ø Each CDB must go to multiple functional units high capacitance, high wiring density Ø Number of functional units that can complete per cycle limited to one! Ø Multiple CDBs more FU logic for parallel assoc stores Ø Non-precise interrupts! Ø We will address this later Dr. Amr Talaat Elect 707

Ø Sect 5 th Edition 3. 4 & 3. 5 Dr. Amr Talaat Elect 707