Chapter 2 Power Electronic Devices Bipolar Transistor BJT

Chapter 2 Power Electronic Devices

Bi-polar Transistor (BJT) (C) (C) IC Collector (B) Base N P N VCB IB (B) VCE (B) VBE Emitter IE (E) (E)

(C) Characteristics of Bi-polar Transistor IC VCB IB VCE (B) VBE IE IB Saturation Region IC (E) IB 1 IB 2< IB 1 Linear Region IB= 0 V 0. 6 BE Base Characteristics Cut Off Region VCE Collector Characteristics

IC IB max IC RL VCC RL IB (1) V CE V CC (2) IB = 0 VCC At point (1) VCE is very small Closed switch Open switch At point (2) IC is very small VCE

Main Features of BJT • Current controlled device – Base current must be present during the closing period – High base losses • Low current gain in the saturation region • Can operate at high frequencies

Field Effect Transistor (FET)

Main Features of FET • Voltage controlled device • Low gate losses

Thyristors (Four Layer Diode)

Thyristors [Silicon Controlled Rectifier (SCR)] Anode (A) IA Ig = max Ig > 0 Gate (G) VRB Ig = 0 Ih V AK Cathode (K) V TO VBO

Closing Conditions of SCR 1. Positive anode to cathode voltage (VAK) 2. Maximum triggering pulse is applied (Ig) Anode (A) Gate (G) Cathode (K) Closing angle is a

Opening Conditions of SCR 1. Anode current is below the holding value (Ih) VRB IA Ig = 0 Ih V AK Opening angle is b

Ratings of Power Electronic Devices • Steady State Circuit ratings: • The current and voltage of the circuit should always be less than the device ratings.

Ratings of Power Electronic Devices • Junction temperature: Losses inside solid-state devices are due to impurities of their material as well as the operating conditions of their circuits.

Ratings of Power Electronic Devices • During the conduction period, the voltage drop across the solid-state device is about one volt. This voltage drop multiplied by the current inside the device produces losses. • When the device is in the blocking mode (open), a small amount of leakage current flows inside the device which also produces losses. • The gate circuits of the SCRs and FETs, and the base circuits of the transistors, produce losses due to their triggering signals. • Every time the solid state device is turned on or off, switching losses are produced. These losses are usually higher for faster devices, and for devices operating in high frequency modes.

Ratings of Power Electronic Devices • Surge current: It is the absolute maximum of the non-repetitive impulse current

Ratings of Power Electronic Devices • Switching time: • Turn-on time is the interval between applying the triggering signal and the turn-on of the device. • The turn-off time is the interval from the onstate to the off-state. • The larger the switching time the smaller is the operating frequency of the circuit.

Ratings of Power Electronic Devices • Critical rate of rise of current (or maximum di/dt): A solid-state device can be damaged if the di/dt of the circuit exceeds the maximum allowable value of the device. di/dt damage can occur even if the current is below the surge limit of the device. To protect the device from this damage, a snubbing circuit for di/dt must be used.

Ratings of Power Electronic Devices • Critical rate of rise of voltage (or maximum dv/dt): When dv/dt across a device exceeds its allowable limit, the device is forced to close. This is a form of false triggering. It may lead to excessive current or excessive di/dt. To protect the device against excessive dv/dt, a snubbing circuit for dv/dt must be used.

di/dt and dv/dt Protection R s Cs + - Ls V Load © M. A. El-Sharkawi, University of Washington 32

Closing Switch Cs + - Rs I 2 Ls V I Load 1 Load impedance © M. A. El-Sharkawi, University of Washington 33

Closing Switch: Analysis of I 1 Ls V I Load 1 © M. A. El-Sharkawi, University of Washington LL , R L , C L 34

Closing Switch: Analysis of I 1 Ls V I Load 1 © M. A. El-Sharkawi, University of Washington 35

Snubbing Circuit: Ls Worst Scenario for Maximum di/dt: When the load capacitor is not charged at t=0 © M. A. El-Sharkawi, University of Washington 36

Closing Switch: Analysis of I 2 The fully charged cap discharges after the switch is closed Cs + - Rs Ls V I 2 Load © M. A. El-Sharkawi, University of Washington 37

Closing Switch: Analysis of I 2 Cs + - Rs Ls V At t = 0 I 2 Load © M. A. El-Sharkawi, University of Washington 38

Opened Switch Rs Cs + - Ls V I Load 3 Load impedance © M. A. El-Sharkawi, University of Washington 39

Opened Switch Cs + - Rs Ls V I 3 © M. A. El-Sharkawi, University of Washington Load 40

Opened Switch Assume the caps are initially discharged Cs + - Rs Ls V © M. A. El-Sharkawi, University of Washington I 3 Load 41

Selection of the Snubbing Circuit Parameters Step 1: Compute snubbing inductance Step 2: Compute snubbing Resistance Step 3: Compute snubbing Capacitance © M. A. El-Sharkawi, University of Washington 42