Chapter 2 Interconnect Analysis Delay Modeling Prof Lei

Chapter 2 Interconnect Analysis Delay Modeling Prof. Lei He Electrical Engineering Department University of California, Los Angeles URL: eda. ee. ucla. edu Email: lhe@ee. ucla. edu 1

Outline p Delay models Ø RC tree Elmore delay (First Order) Ø Second Order Analysis (S 2 P algorithm) Ø Gate delay 2

Input-to-Output Propagation Delay The circuit delay in VLSI circuits consists of two components: n n The 50% propagation delay of the driving gates (known as the gate delay) The delay of electrical signals through the wires (known as the interconnect delay) 3

Lumped vs Distributed Interconnect Model Lumped Distributed r r R C c r c c How to analyze the delay for each model? 4

Lumped RC Model u(t) R v(t) C Impulse response and step response of a lumped RC circuit 5

Analysis of Lumped RC Model R S-domain ckt equation (current equation) C Frequency domain response for step-input Frequency domain response for impulse match initial state: Time domain response for step-input: v 0 v 0(1 -e. RC/T) Time domain response for impulse: 6

50% Delay for lumped RC model 1 v V(t) R C 1 0. 5 50% delay How about more complex circuits? 7

Distributed RC-Tree 2 R 1 C 2 1 s 4 R 3 C 4 C 1 3 C 3 Ri i Ci n n n The network has a single input node All capacitors between node and ground The network does not contain any resistive loop 8

RC-tree Property 2 R 1 C 2 1 s 4 R 3 C 4 C 1 3 C 3 Ri i Ci n n Unique resistive path between the source node s and any other node i of the network path resistance Rii Example: R 44=R 1+R 3+R 4 9

RC-tree Property 2 R 1 C 2 1 s 4 R 3 C 4 C 1 3 C 3 Ri i Ci n Extended to shared path resistance Rik: Example: Ri 4=R 1+R 3 Ri 2=R 1 10

Elmore Delay p p p Assuming: – Each node is initially discharged to ground – A step input is applied at time t=0 at node s The Elmore delay at node i is: Theorem: The Elmore delay is equivalent to the first-order time constant of the network – – Proven acceptable approximation of the real delay Powerful mechanism for a quick estimate 11

Example 2 R 1 C 2 1 s 4 R 3 C 4 C 1 3 C 3 Ri i Ci n Elmore delay at node i is 12

Interpretation of Elmore Delay Definition n n h(t) = impulse response TD = mean of h(t) H(t) = step response = Interpretation n n median of h(t) (T 50%) H(t) = output response (step process) h(t) = rate of change of H(t) T 50%= median of h(t) Elmore delay approximates the median of h(t) by the mean of h(t) 13

Elmore Delay Approximation 14

RC-chain (or ladder) Special case: Shared-path resistance R 1 R 2 RN Vin VN C 1 C 2 CN 15

RC-Chain Delay R R R VN Vin R=r · L/N C=c·L/N C C C – Delay of wire is quadratic function of its length – Delay of distributed rc-line is half of lumped RC 16

Outline p Delay models Ø RC tree Elmore delay (First Order) Ø Second Order Analysis (S 2 P algorithm) Ø Gate delay 17

Stable 2 -Pole RC delay calculation (S 2 P) The Elmore delay is the metric of choice for performance-driven design applications due to its simple, explicit form and ease with which sensitivity information can be calculated However, for deep submicron technologies (DSM), the accuracy of the Elmore delay is insufficient 18

Moments of H(s) are coefficients of the Taylor’s Expansion of H(s) about s=0 19

Driving Point Admittance Let Y(s) be an driving point admittance function of a general RC circuit. Consider its representation in terms poles and residues where q is the exact order of the circuit Moments of Y(s) can be written as: 20

S 2 P Algorithm Compute m 1, m 2, m 3 and m 4 for Y(s) Find the two poles at the driving point admittance as follows: To match the voltage moments at the response nodes, choose and the S 2 P approximation is then expressed as: Note that m 0* and m 1* are the moments of H(s). m 0* is the Elmore delay. 21

S 2 P Vs. Elmore Delay 22

Outline p Delay models Ø RC tree Elmore delay (First Order) Ø Second Order Analysis (S 2 P algorithm) Ø Gate delay 23

Gate Delay and Output Transition Time The gate delay and the output transition time are functions of both input slew and the output load 24

General Model of a Gate 25

Definitions Output Transition Time Vout Wp Vin Vout CM tin Wn Cdiff Cload tout Vin 90% 10% Time Cout Gate Delay 26

Output Response for Different Loads 27

Output Transition time (s) Output Transition Time Input Transition Time (s) 10 -10 CLoad (F) 10 -14 Output transition time as a function of input transition time and output load 28

ASIC Cell Delay Model p Three approaches for gate propagation delay computation are based on: Delay look-up tables – K-factor approximation – Effective capacitance – p p Delay look-up table is currently in wide use especially in the ASIC design flow Effective capacitance promises to be more accurate when the load is not purely capacitive 29

Table Look-Up Method 115 p. S n What is the delay when Cload is 505 f F and Tin is 90 p. S? 30

Output Transition time (s) K-factor Approximation Input Transition Time (s) 10 -10 CLoad (F) 10 -14 We can fit the output transition time v. s. input transition time and output load as a polynomial function, e. g. A similar equation gives the gate delay 31

One Dimensional Table Linear model 32

Two Dimensional Table D 2 D 1 D 3 D 4 Quadratic model 33

Second-order RC-p Model n Using Taylor Expansion around s = 0 34

Second-order RC-p Model (Cont’d) n n This equation requires creation of a fourdimensional table to achieve high accuracy This is however costly in terms of memory space and computational requirements 35

Effective Capacitance Approach The “Effective Capacitance” approach attempts to find a single capacitance value that can be replaced instead of the RC-p load such that both circuits behave similarly during transition 36

Output Response for Effective Capacitance 37

Effective Capacitance (Cont’d) 38

Effective Capacitance (Cont’d) 0<k<1 n Because of the shielding effect of the interconnect resistance , the driver will only “see” a portion of the far-end capacitance C 2 Rp 0 k=1 Rp ∞ k=0 39

Effective Capacitance for Different Resistive Shielding 40

Macy’s Approach Assumption: If two circuits have the same loads and output transition times, then their effective capacitances are the same => the effective capacitance is only a function of the output transition time and the load 41

Macy’s Iterative Solution 1. Compute a from C 1 and C 2 2. Choose an initial value for Ceff 3. Compute Tout for the given Ceff and Tin 4. Compute b 5. Compute g from a and b 6. Find new Ceff 7. Go to step 3 until Ceff converges 42

Summary p Delay model – Elmore delay – Gate delay: look-up table, k-factor approximation, effective capacitance 43

References l R. Macys and S. Mc. Cormick, “A New Algorithm for Computing the “Effective Capacitance” in Deep Sub-micron Circuits”, Custom Integrated Circuits Conference 1998, pp. 313 -316 l J. Qian, S. Pullela, and L. T. Pileggi, "Modeling the "effective capacitance" for the RC interconnect of CMOS gates, " IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, pp. 1526 -1535, Dec. 1994. l Jason Cong , Lei He , Cheng-Kok Koh , Patrick H. Madden, Performance optimization of VLSI interconnect layout, Integration, the VLSI Journal, v. 21 n. 1 -2, p. 1 -94, Nov. 1996 (Section 2. 1 -2. 2) l W. C. Elmore, “The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers”, Journal of Applied Physics, 1948. l Jorge Rubinstein, and etc. “Signal Delay in RC Tree Networks”, TCAD'83 l Emrah Acar, Altan Odabasioglu, Mustafa Celik, and Lawrence T. Pileggi. 1999. “S 2 P: A Stable 2 -Pole RC Delay and Coupling Noise Metric”. In Proceedings of the Ninth Great Lakes Symposium on VLSI(GLS '99). 44