Chapter 14 Instruction Level Parallelism and Superscalar Processors

Chapter 14 Instruction Level Parallelism and Superscalar Processors

What is Superscalar?

Why Superscalar?

General Superscalar Organization

Superpipelined

Superscalar v Superpipeline

Limitations

True Data Dependency

Procedural Dependency

Resource Conflict

Effect of Dependencies

Design Issues

Instruction Issue Policy

In-Order Issue In-Order Completion

In-Order Issue In-Order Completion (Diagram)

In-Order Issue Out-of-Order Completion

In-Order Issue Out-of-Order Completion (Diagram)

Out-of-Order Issue Out-of-Order Completion

Out-of-Order Issue Out-of-Order Completion (Diagram)

Antidependency

Reorder Buffer

Register Renaming

Register Renaming example

Machine Parallelism

Speedups of Machine Organizations Without Procedural Dependencies

Branch Prediction

RISC - Delayed Branch

Superscalar Execution

Superscalar Implementation

Pentium 4

Pentium 4 Block Diagram

Pentium 4 Operation

Pentium 4 Pipeline

Pentium 4 Pipeline Operation (1)

Pentium 4 Pipeline Operation (2)

Pentium 4 Pipeline Operation (3)

Pentium 4 Pipeline Operation (4)

Pentium 4 Pipeline Operation (5)

Pentium 4 Pipeline Operation (6)

ARM CORTEX-A 8

Instruction Fetch Unit

Instruction Decode Unit

Instruction Processing Stages

Integer Execution Unit

Load/store pipeline

SIMD and Floating-Point Pipeline

Required Reading