Chapter 10 Trends in Computer Architecture 10 1

  • Slides: 41
Download presentation
Chapter 10 - Trends in Computer Architecture 10 -1 Principles of Computer Architecture Miles

Chapter 10 - Trends in Computer Architecture 10 -1 Principles of Computer Architecture Miles Murdocca and Vincent Heuring Chapter 10: Trends in Computer Architecture Department of Information Technology, Radford University ITEC 352 Computer Organization

Chapter 10 - Trends in Computer Architecture 10 -2 Chapter Contents 10. 1 Quantitative

Chapter 10 - Trends in Computer Architecture 10 -2 Chapter Contents 10. 1 Quantitative Analyses of Program Execution 10. 2 From CISC to RISC 10. 3 Pipelining the Datapath 10. 4 Overlapping Register Windows 10. 5 Multiple Instruction Issue (Superscalar) Machines – The Power. PC 10. 6 Case Study: The Power. PC™ 601 as a Superscalar Architecture 10. 7 VLIW Machines 10. 8 Case Study: The Intel IA-64 (Merced) Architecture 10. 9 Parallel Architecture 10. 10 Case Study: Parallel Processing in the Sega Genesis Department of Information Technology, Radford University ITEC 352 Computer Organization

Chapter 10 - Trends in Computer Architecture 10 -3 Instruction Frequency • Frequency of

Chapter 10 - Trends in Computer Architecture 10 -3 Instruction Frequency • Frequency of occurrence of instruction types for a variety of languages. The percentages do not sum to 100 due to roundoff. (Adapted from Knuth, D. E. , An Empirical Study of FORTRAN Programs, Software—Practice and Experience, 1, 105 -133, 1971. ) Department of Information Technology, Radford University ITEC 352 Computer Organization

Chapter 10 - Trends in Computer Architecture 10 -4 Complexity of Assignments • Percentages

Chapter 10 - Trends in Computer Architecture 10 -4 Complexity of Assignments • Percentages showing complexity of assignments and procedure calls. (Adapted from Tanenbaum, A. , Structured Computer Organization, 4/e, Prentice Hall, Upper Saddle River, New Jersey, 1999. ) Department of Information Technology, Radford University ITEC 352 Computer Organization

Chapter 10 - Trends in Computer Architecture 10 -5 Speedup and Efficiency • Speedup

Chapter 10 - Trends in Computer Architecture 10 -5 Speedup and Efficiency • Speedup S is the ratio of the time needed to execute a program without an enhancement to the time required with an enhancement. • Time T is computed as the instruction count IC times the number of cycles per instruction CPI times the cycle time t. • Substituting T into the speedup percentage calculation above yields: Department of Information Technology, Radford University ITEC 352 Computer Organization

Chapter 10 - Trends in Computer Architecture 10 -6 Example • Example: Estimate the

Chapter 10 - Trends in Computer Architecture 10 -6 Example • Example: Estimate the speedup obtained by replacing a CPU having an average CPI of 5 with another CPU having an average CPI of 3. 5, with the clock period increased from 100 ns to 120 ns. • The previous equation becomes: Department of Information Technology, Radford University ITEC 352 Computer Organization

Chapter 10 - Trends in Computer Architecture 10 -7 Four-Stage Instruction Pipeline Department of

Chapter 10 - Trends in Computer Architecture 10 -7 Four-Stage Instruction Pipeline Department of Information Technology, Radford University ITEC 352 Computer Organization

Chapter 10 - Trends in Computer Architecture 10 -8 Pipeline Behavior • Pipeline behavior

Chapter 10 - Trends in Computer Architecture 10 -8 Pipeline Behavior • Pipeline behavior during a memory reference and during a branch. Department of Information Technology, Radford University ITEC 352 Computer Organization

Chapter 10 - Trends in Computer Architecture 10 -9 Filling the Load Delay Slot

Chapter 10 - Trends in Computer Architecture 10 -9 Filling the Load Delay Slot • SPARC code, (a) with a nop inserted, and (b) with srl migrated to nop position. Department of Information Technology, Radford University ITEC 352 Computer Organization

Chapter 10 - Trends in Computer Architecture 10 -10 Call-Return Behavior • Call-return behavior

Chapter 10 - Trends in Computer Architecture 10 -10 Call-Return Behavior • Call-return behavior as a function of nesting depth and time (Adapted from Stallings, W. , Computer Organization and Architecture: Designing for Performance, 4/e, Prentice Hall, Upper Saddle River, 1996). Department of Information Technology, Radford University ITEC 352 Computer Organization

Chapter 10 - Trends in Computer Architecture 10 -11 SPARC Registers • User view

Chapter 10 - Trends in Computer Architecture 10 -11 SPARC Registers • User view of RISC I registers. Department of Information Technology, Radford University ITEC 352 Computer Organization

Chapter 10 - Trends in Computer Architecture 10 -12 Overlapping Register Windows Department of

Chapter 10 - Trends in Computer Architecture 10 -12 Overlapping Register Windows Department of Information Technology, Radford University ITEC 352 Computer Organization

10 -13 Chapter 10 - Trends in Computer Architecture Example: Compiled C Program •

10 -13 Chapter 10 - Trends in Computer Architecture Example: Compiled C Program • Source code for C program to be compiled with gcc. Department of Information Technology, Radford University ITEC 352 Computer Organization

10 -14 Chapter 10 - Trends in Computer Architecture gcc Generated SPARC Code Department

10 -14 Chapter 10 - Trends in Computer Architecture gcc Generated SPARC Code Department of Information Technology, Radford University ITEC 352 Computer Organization

10 -15 Chapter 10 - Trends in Computer Architecture gcc Generated SPARC Code (cont’)

10 -15 Chapter 10 - Trends in Computer Architecture gcc Generated SPARC Code (cont’) Department of Information Technology, Radford University ITEC 352 Computer Organization

10 -16 Chapter 10 - Trends in Computer Architecture Effect of Compiler Optimization •

10 -16 Chapter 10 - Trends in Computer Architecture Effect of Compiler Optimization • SPARC code generated with the -O optimization flag: Department of Information Technology, Radford University ITEC 352 Computer Organization

10 -17 Chapter 10 - Trends in Computer Architecture The Power. PC 601 Architecture

10 -17 Chapter 10 - Trends in Computer Architecture The Power. PC 601 Architecture Department of Information Technology, Radford University ITEC 352 Computer Organization

Chapter 10 - Trends in Computer Architecture 10 -18 128 -Bit IA-64 Instruction Word

Chapter 10 - Trends in Computer Architecture 10 -18 128 -Bit IA-64 Instruction Word Department of Information Technology, Radford University ITEC 352 Computer Organization

10 -19 Chapter 10 - Trends in Computer Architecture Parallel Speedup and Amdahl’s Law

10 -19 Chapter 10 - Trends in Computer Architecture Parallel Speedup and Amdahl’s Law • In the context of parallel processing, speedup can be computed: • Amdahl’s law, for p processors and a fraction f of unparallelizable code: • For example, if f = 10% of the operations must be performed sequentially, then speedup can be no greater than 10 regardless of how many processors are used: Department of Information Technology, Radford University ITEC 352 Computer Organization

Chapter 10 - Trends in Computer Architecture 10 -20 Efficiency and Throughput • Efficiency

Chapter 10 - Trends in Computer Architecture 10 -20 Efficiency and Throughput • Efficiency is the ratio of speedup to the number of processors used. For a speedup of 5. 3 with 10 processors, the efficiency is: • Throughput is a measure of how much computation is achieved over time, and is of special concern for I/O bound and pipelined applications. For the case of a four stage pipeline that remains filled, in which each pipeline stage completes its task in 10 ns, the average time to complete an operation is 10 ns even though it takes 40 ns to execute any one operation. The overall throughput for this situation is then: Department of Information Technology, Radford University ITEC 352 Computer Organization

Chapter 10 - Trends in Computer Architecture 10 -21 Flynn Taxonomy • Classification of

Chapter 10 - Trends in Computer Architecture 10 -21 Flynn Taxonomy • Classification of architectures according to the Flynn taxonomy: (a) SISD; (b) SIMD; (c) MIMD; (d) MISD. Department of Information Technology, Radford University ITEC 352 Computer Organization

10 -22 Chapter 10 - Trends in Computer Architecture Network Topologies • Network topologies:

10 -22 Chapter 10 - Trends in Computer Architecture Network Topologies • Network topologies: (a) crossbar; (b) bus; (c) ring; (d) mesh; (e) star; (f) tree; (g) perfect shuffle; (h) hypercube. Department of Information Technology, Radford University ITEC 352 Computer Organization

Chapter 10 - Trends in Computer Architecture 10 -23 Crossbar • Internal organization of

Chapter 10 - Trends in Computer Architecture 10 -23 Crossbar • Internal organization of a crossbar. Department of Information Technology, Radford University ITEC 352 Computer Organization

Chapter 10 - Trends in Computer Architecture 10 -24 Crosspoint Settings • (a) Crosspoint

Chapter 10 - Trends in Computer Architecture 10 -24 Crosspoint Settings • (a) Crosspoint settings for connections 0 ® 3 and 3 ® 0; (b) adjusted settings to accommodate connection 1 ® 1. Department of Information Technology, Radford University ITEC 352 Computer Organization

Chapter 10 - Trends in Computer Architecture 10 -25 Three-Stage Clos Network Department of

Chapter 10 - Trends in Computer Architecture 10 -25 Three-Stage Clos Network Department of Information Technology, Radford University ITEC 352 Computer Organization

10 -26 Chapter 10 - Trends in Computer Architecture 12 -Channel Three. Stage Clos

10 -26 Chapter 10 - Trends in Computer Architecture 12 -Channel Three. Stage Clos Network with n = p =6 Department of Information Technology, Radford University ITEC 352 Computer Organization

10 -27 Chapter 10 - Trends in Computer Architecture 12 Channel Three. Stage Clos

10 -27 Chapter 10 - Trends in Computer Architecture 12 Channel Three. Stage Clos Network with n = p =2 Department of Information Technology, Radford University ITEC 352 Computer Organization

10 -28 Chapter 10 - Trends in Computer Architecture 12 -Channel Three-Stage Clos Network

10 -28 Chapter 10 - Trends in Computer Architecture 12 -Channel Three-Stage Clos Network with n = p = 4 Department of Information Technology, Radford University ITEC 352 Computer Organization

Chapter 10 - Trends in Computer Architecture 10 -29 12 -Channel Three-Stage Clos Network

Chapter 10 - Trends in Computer Architecture 10 -29 12 -Channel Three-Stage Clos Network with n = p = 3 Department of Information Technology, Radford University ITEC 352 Computer Organization

Chapter 10 - Trends in Computer Architecture 10 -30 C function computes (x 2

Chapter 10 - Trends in Computer Architecture 10 -30 C function computes (x 2 + y 2) ´ y 2 Department of Information Technology, Radford University ITEC 352 Computer Organization

10 -31 Chapter 10 - Trends in Computer Architecture Dependency Graph • (a) Control

10 -31 Chapter 10 - Trends in Computer Architecture Dependency Graph • (a) Control sequence for C program; (b) dependency graph for C program. Department of Information Technology, Radford University ITEC 352 Computer Organization

10 -32 Chapter 10 - Trends in Computer Architecture Matrix Multiplication • (a) Problem

10 -32 Chapter 10 - Trends in Computer Architecture Matrix Multiplication • (a) Problem setup for Ax = b; (b) equations for computing the bi. Department of Information Technology, Radford University ITEC 352 Computer Organization

10 -33 Chapter 10 - Trends in Computer Architecture Matrix Multiplication Dependency Graph Department

10 -33 Chapter 10 - Trends in Computer Architecture Matrix Multiplication Dependency Graph Department of Information Technology, Radford University ITEC 352 Computer Organization

Chapter 10 - Trends in Computer Architecture 10 -34 The Connection Machine CM-1 •

Chapter 10 - Trends in Computer Architecture 10 -34 The Connection Machine CM-1 • Block diagram of the CM-1 (Adapted from Hillis, W. D. , The Connection Machine, The MIT Press, 1985). Department of Information Technology, Radford University ITEC 352 Computer Organization

Chapter 10 - Trends in Computer Architecture 10 -35 CM-1 Router Network • A

Chapter 10 - Trends in Computer Architecture 10 -35 CM-1 Router Network • A four-space hypercube for the router network. Department of Information Technology, Radford University ITEC 352 Computer Organization

Chapter 10 - Trends in Computer Architecture 10 -36 CM-1 Processing Element Department of

Chapter 10 - Trends in Computer Architecture 10 -36 CM-1 Processing Element Department of Information Technology, Radford University ITEC 352 Computer Organization

Chapter 10 - Trends in Computer Architecture 10 -37 The Connection Machine CM-5 Department

Chapter 10 - Trends in Computer Architecture 10 -37 The Connection Machine CM-5 Department of Information Technology, Radford University ITEC 352 Computer Organization

Chapter 10 - Trends in Computer Architecture 10 -38 Partitions on the CM-5 Department

Chapter 10 - Trends in Computer Architecture 10 -38 Partitions on the CM-5 Department of Information Technology, Radford University ITEC 352 Computer Organization

Chapter 10 - Trends in Computer Architecture 10 -39 Fat Tree Department of Information

Chapter 10 - Trends in Computer Architecture 10 -39 Fat Tree Department of Information Technology, Radford University ITEC 352 Computer Organization

10 -40 Chapter 10 - Trends in Computer Architecture Parallel Processing in Sega Genesis

10 -40 Chapter 10 - Trends in Computer Architecture Parallel Processing in Sega Genesis • External view of the Sega Genesis home video game system. Department of Information Technology, Radford University ITEC 352 Computer Organization

Chapter 10 - Trends in Computer Architecture 10 -41 Sega Genesis Architecture • External

Chapter 10 - Trends in Computer Architecture 10 -41 Sega Genesis Architecture • External view of the Sega Genesis home video game system. Department of Information Technology, Radford University ITEC 352 Computer Organization