Chapter 10 Computer Design Basics Henry Hexmoor 1

Chapter 10 Computer Design Basics Henry Hexmoor 1

10 -1 § Computer Specification • Instruction Set Architecture (ISA) - the specification of a computer's appearance to a programmer at its lowest level • Computer Architecture - a high-level description of the hardware implementing the computer derived from the ISA • The architecture usually includes additional specifications such as speed, cost, and reliability. Henry Hexmoor 2

Introduction (continued) § Simple computer architecture decomposed into: • Datapath for performing operations • Control unit for controlling datapath operations § A datapath is specified by: • A set of registers • The microoperations performed on the data stored in the registers • A control interface Henry Hexmoor 3

Datapaths 10 -2 § Guiding principles for basic datapaths: • The set of registers § Collection of individual registers § A set of registers with common access resources called a register file § A combination of the above • Microoperation implementation § One or more shared resources for implementing microoperations § Buses - shared transfer paths § Arithmetic-Logic Unit (ALU) - shared resource for implementing arithmetic and logic microoperations § Shifter - shared resource for implementing shift microoperations Henry Hexmoor 4

Datapath Example Figure 10 -1 § Four parallel-load registers (R 0 -R 3) § Two mux-based register selectors § Register destination decoder § Mux B for external constant input § Buses A and B with external address and data outputs § ALU and Shifter with Mux F for output select § Mux D for external data input § Logic for generating status bits V, C, N, Z Henry Hexmoor Load enable A select Write D data n Load A address B address 2 2 R 0 n B select n Load R 1 0 1 MUX 2 3 n n 0 1 Load 2 3 R 2 n n Load MUX R 3 n 0 1 2 3 n n Decoder D address 2 Constant in n Destination select n MB select Register file A data 1 0 MUX B Bus A A n C N Z B G select A B 4 S 2: 0 || Cin Arithmetic/logic unit (ALU) G 0 1 MUX F F n MF select 5 n MD select Bus D H select 2 S IR 0 Out n B Shifter IL 0 H n n Zero Detect Address Out Data n Bus B V B data n 0 1 MUX D Function unit n Data In

Datapath Example: Performing a Microoperation Load enable § Microoperation: R 0 ← R 1 + R 2 § Apply 01 to A select to place contents of R 1 onto Bus A § Apply 10 to B select to place contents of R 2 onto B data and apply 0 to MB select to place B data on Bus B § Apply 0010 to G select to perform addition G = Bus A + Bus B § Apply 0 to MF select and 0 to MD select to place the value of G onto BUS D § Apply 00 to Destination select to enable the Load input to R 0 § Apply 1 to Load Enable to force the Load input to R 0 to 1 so that R 0 is loaded on the clock pulse (not shown) § The overall microoperation requires 1 clock cycle Henry Hexmoor A select Write D data n Load A address B address 2 2 R 0 n B select n Load R 1 0 1 MUX 2 3 n n 0 1 Load 2 3 R 2 n n Load MUX R 3 n 0 1 2 3 n n Decoder D address 2 Constant in n Destination select n MB select Register file A data 1 0 MUX B Bus A A n C N Z B G select A B 4 S 2: 0 || Cin Arithmetic/logic unit (ALU) G 0 1 MUX F F n MF select 6 n MD select Bus D H select 2 S IR 0 Out n B Shifter IL 0 H n n Zero Detect Address Out Data n Bus B V B data n 0 1 MUX D Function unit n Data In

Arithmetic Logic Unit (ALU) § In this and the next section, we deal with detailed design of typical ALUs and shifters § Decompose the ALU into: • An arithmetic circuit • A logic circuit • A selector to pick between the two circuits § Arithmetic circuit design • Decompose the arithmetic circuit into: § An n-bit parallel adder § A block of logic that selects four choices for the B input to the adder § See next slide for diagram Henry Hexmoor 7

§ Arithmetic Circuit Design Figure 10 -3 and Table 10 -1 and table 10 -2 (pages There are only four functions of B 435, to select 438) as Y in G = A + Y: • • All 0’s B B All 1’s Cin = 0 G=A+B G=A– 1 Cin = 1 G=A+B+1 G = A + B + 1 Subtraction G=A Cin n A B X n-bit parallel adder n S 0 S 1 Henry Hexmoor B input logic n n G = X Y + Cin Y 8 Cout

Logic Circuit § The text gives a circuit implemented using a multiplexer plus gates implementing: AND, OR, XOR and NOT § Here we custom design a circuit for bit Gi by beginning with a truth table organized as logic operation K-map and assigning (S 1, S 0) codes to AND, OR, etc. § Gi = S 0 Ai Bi + S 1 Ai Bi S 1 S 0 AND OR XOR NOT + S 0 Ai B i + S 1 S 0 Ai Ai B i 0 0 0 1 11 10 § Gate input count for 00 0 1 MUX solution > 29 § Gate input count for 01 0 1 1 1 above circuit < 20 11 1 1 0 0 § Custom design better 10 Henry Hexmoor 0 9 1 1 0

Arithmetic Logic Unit (ALU) § The custom circuit has interchanged the (S 1, S 0) codes for XOR and NOT compared to the MUX circuit. To preserve compatibility with the text, we use the MUX solution. § Next, use the arithmetic circuit, the logic circuit, and a 2 -way multiplexer to form the ALU. See the next slide for the bit slice diagram. § The input connections to the arithmetic circuit and logic circuit have been assigned to prepare for seamless addition of the shifter, keeping the selection codes for the combined ALU and the shifter at 4 bits: • Carry-in Ci and Carry-out Ci+1 go between bits • Ai and Bi are connected to both units • A new signal S 2 performs the arithmetic/logic selection • The select signal entering the LSB of the arithmetic circuit, Cin, is connected to the least significant selection input for the logic circuit, S 0. Henry Hexmoor 10

Arithmetic Logic Unit (ALU) Figure 10 -7 Ci Ci Ai Ai S 0 One stage of B i arithmetic circuit S 0 S 1 Bi Ci 2 -to-1 0 MUX Gi 1 Ai C in +1 S B i One stage of logic circuit S 0 S 1 S 2 § The next most significant select signals, S 0 for the arithmetic circuit and S 1 for the logic circuit, are wired together, completing the two select signals for the logic circuit. § The remaining S 1 completes the three select signals for the arithmetic circuit. Henry Hexmoor 11

Combinational Shifter Parameters 10 -4 § Direction: Left, Right § Number of positions with examples: • Single bit: § 1 position § 0 and 1 positions • Multiple bit: § 1 to n – 1 positions § 0 to n – 1 positions § Filling of vacant positions • Many options depending on instruction set • Here, will provide input lines or zero fill Henry Hexmoor 12

4 -Bit Basic Left/Right Shifter (Figure 10 -8) B 3 B 2 B 1 B 0 Serial output L Serial output R IL IR S S 0 1 2 M U X S 0 1 2 M U X 2 H 3 § Serial Inputs: H 2 H 1 H 0 § Shift Functions: • IR for right shift (S 1, S 0) = 00 Pass B unchanged • IL for left shift 01 Right shift 10 Left shift § Serial Outputs 11 Unused • R for right shift (Same as MSB input) • L for left shift (Same as LSB input) Henry Hexmoor 13

Barrel Shifter (Figure 10 -9) D 3 D 2 D 1 D 0 S 1 3 2 1 0 S 1 S 0 M M U U X X Y 3 Y 2 Y 1 Y 0 § A rotate is a shift in which the bits shifted out are inserted into the positions vacated § The circuit rotates its contents left from 0 to 3 positions depending on S: S = 00 position unchanged S = 10 rotate left by 2 positions S = 01 rotate left by 1 positions S = 11 rotate left by 3 positions § See Table 10 -3 in text for details (page 440) Henry Hexmoor 14

Barrel Shifter (continued) § Large barrel shifters can be constructed by using: 1. Layers of multiplexers - Example 64 -bit: § § Layer 1 shifts by 0, 16, 32, 48 Layer 2 shifts by 0, 4, 8, 12 Layer 3 shifts by 0, 1, 2, 3 See example in section 12 -2 of the text 2. 2 dimensional array circuits designed at the electronic level Henry Hexmoor 15

Datapath Representation 10 -5 § Here we move up one level in the hierarchy from that datapath § The registers, and the multiplexer, decoder, and enable hardware for accessing them become a register file § A register file is an array of fast registers § The ALU, shifter, Mux F and status hardware become a function unit § The remaining muxes and buses which handle data transfers are at the new level of the hierarchy Henry Hexmoor n D data Write D address 2 mx n Register file m m A address B address A data Constant in B data n n n 1 0 MUX B MB select Bus A FS V C N Z 4 m A n Bus B n Address out Data out B Function unit F n MD select 16 0 1 MUX D n Data in

Datapath Representation (continued) n § In the register file: • Multiplexer select inputs become A address and B address • Decoder input becomes D address • Multiplexer outputs become A data and B data • Input data to the registers becomes D data • Load enable becomes write § The register file now appears like a memory based on clocked flipflops (the clock is not shown) § The function unit labeling is quite straightforward except for FS Henry Hexmoor m m D data Write D address 2 mx n Register file A address B address A data Constant in B data n n n 1 0 MUX B MB select Bus A FS V C N Z 4 m A n Bus B n Address out Data out B Function unit F n MD select 17 0 1 MUX D n Data in

Definition of Function Unit Select (FS) Codes G Select, H Select, and MF (Table 10 -4, page 443)) in T of FS Codes FS(3: 0) MF Select 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 Henry Hexmoor 0 0 0 1 1 1 G H Select(3: 0) 0000 0001 0010 0011 0100 0101 0110 0111 1 X 00 1 X 01 1 X 10 1 X 11 XXXX XX XX XX 00 01 10 Microoperation F ¬ A F ¬A + 1 F ¬A + B + 1 F ¬A - 1 F ¬A F ¬ A ÙB F ¬ A ÚB F ¬ A ÅB F ¬A F ¬B F ¬ sr B F ¬ sl B 18 Boolean Equations: MF = F 3 F 2 Gi = F i Hi = F i

The Control Word § The datapath has many control inputs § The signals driving these inputs can be defined and organized into a control word § To execute a microinstruction, we apply control word values for a clock cycle. For most microoperations, the positive edge of the clock cycle is needed to perform the register load § The datapath control word format and the field definitions are shown on the next slide Henry Hexmoor 19

The Control Word Fields 15 14 13 12 11 10 9 8 DA § Fields • • AA BA 7 6 5 M B 4 3 2 1 0 MR D W FS Control word DA – D Address (destination) AA – A Address BA – B Address (source for MUXB MB – Mux B (constant/source FS – Function Select MD – Mux D RW – Register Write § The connections to datapath are shown in the next slide Henry Hexmoor 20

Control Word Block Diagram (Figure 10 -11) n D data RW 0 Write 15 DA 14 13 D address 12 AA 11 10 A address 8 x n Register file 9 8 BA 7 B address A data n B data n n Constant in MB 6 1 0 MUX B Bus A n n Bus B A V C N Z 5 4 FS 3 2 n n 0 1 MUX D Bus D Henry Hexmoor Data out B Function unit MD 1 Address out 21 Data in

Control Word Encoding Table 10 -5 Encoding of Control W DA, AA, BA MB FS Function Code Function R 0 R 1 R 2 R 3 R 4 R 5 R 6 R 7 Register 0 Constant 1 000 001 010 011 100 101 110 111 Henry Hexmoor MD Code F ¬A 0000 0001 F ¬A + 1 0010 F ¬A + B F ¬ A + B + 1 0011 F ¬A + B 0100 F ¬ A + B + 1 0101 F ¬A - 1 0110 F ¬A 0111 F ¬ A ÙB 1000 F ¬ A ÚB 1001 1010 F ¬A ÅB 1011 F ¬A 1100 F ¬B 1101 F ¬ sr B 1110 F ¬ sl B 22 RW Function Code Function 0 Data In 1 No write 0 Write 1

Microoperations for the Datapath Symbolic Representation Table 10 -6 R 1¬R 2 –R 3 R 4 ¬ sl R 6 R 7¬R 7 + 1 R 1¬R 0 + 2 Data out ¬ R 3 R 4 ¬ Data in R 5¬ 0 Henry Hexmoor DA AA BA MB FS MD RW R 1 R 4 R 7 R 1 —— R 4 R 5 R 2 — R 7 R 0 R 3 R 6 — — R 3 Register Re gister Con stant Register — Register F = A +B +1 F = sl B F = A +1 F = A +B — — F = A ÅB Function Func tion — Data in Function Write No Wr ite Write —— R 0 23

Microoperations for the Datapath - Binary Representation. Binary Co m Microoperations from Ta o Table 10 -7 Microoperation DA AA BA MB FS MD RW R 1¬R 2 –R 3 R 4 ¬ sl R 6 R 7¬R 7 + 1 R 1¬R 0 + 2 Data out ¬ R 3 R 4 ¬ D ata in R 5¬ 0 001 100 111 001 XXX 100 101 010 XXX 111 000 XXX 000 011 110 XXX 011 XXX 000 0 1 0 X 0 0101 1110 0001 0010 0 0 X 1 0 1 1 XXXX 1010 § Results of simulation of the above on the next slide Henry Hexmoor 24

Datapath Simulation Figure 10 -12 clock 2 4 3 7 4 1 2 0 7 0 BA 3 6 0 FS 5 14 1 DA 1 1 AA Constant_in X 5 0 6 4 3 0 2 X 8 7 5 10 MB Address_out 2 0 7 0 Data_out 3 6 0 2 18 Data_in 3 0 18 MD RW reg 0 Henry Hexmoor reg 1 0 1 reg 2 2 reg 3 3 reg 4 4 reg 5 5 reg 6 6 reg 7 7 Status_bits 2 255 2 12 18 0 25 0 1 X

Instruction Set Architecture (ISA) for Simple Computer (SC) 10 -7 § A programmable system uses a sequence of instructions to control its operation § An typical instruction specifies: • • Operation to be performed Operands to use, and Where to place the result, or Which instruction to execute next § Instructions are stored in RAM or ROM as a program § The addresses for instructions in a computer are provided by a program counter (PC) that can • Count up • Load a new address based on an instruction and, optionally, status information Henry Hexmoor 26

Instruction Set Architecture (ISA) (continued) § The PC and associated control logic are part of the Control Unit § Executing an instruction - activating the necessary sequence of operations specified by the instruction § Execution is controlled by the control unit and performed: • In the datapath • In the control unit • In external hardware such as memory or input/output Henry Hexmoor 27

ISA: Storage Resources Figure 10 -13 § The storage resources are "visible" to the programmer at the lowest software level (typically, machine or assembly language) § Storage resources for the SC => § Separate instruction and data memories imply "Harvard architecture" § Done to permit use of single clock cycle per instruction implementation § Due to use of "cache" in modern computer architectures, is a fairly realistic model Henry Hexmoor Program counter (PC) Instruction memory 215 x 16 Register file 8 x 16 Data memory 215 x 16 28

ISA: Instruction Format § A instruction consists of a bit vector § The fields of an instruction are subvectors representing specific functions and having specific binary codes defined § The format of an instruction defines the subvectors and their function § An ISA usually contains multiple formats § The SC ISA contains the three formats presented on the next slide Henry Hexmoor 29

ISA: Instruction Format Figure 10 -14 15 9 8 6 5 Destination register (DR) Opcode 3 2 Source register A (SA) 0 Source register B (SB) (a) Register 15 9 8 6 5 Destination register (DR) Opcode 3 2 Source register A (SA) 0 Operand (OP) (b) Immediate 15 9 8 Opcode 6 5 Address (AD) (Left) 3 2 Source register A (SA) 0 Address (AD) (Right) (c) Jump and Branch § § The three formats are: Register, Immediate, and Jump and Branch All formats contain an Opcode field in bits 9 through 15. The Opcode specifies the operation to be performed More details on each format are provided on the next three slides Henry Hexmoor 30

ISA: Instruction Format (continued) 15 9 8 Opcode 6 5 Destination register (DR) 3 2 Source register A (SA) (a) Register 0 Source register B (SB) § This format supports instructions represented by: • R 1 ← R 2 + R 3 • R 1 ← sl R 2 § There are three 3 -bit register fields: • DR - specifies destination register (R 1 in the examples) • SA - specifies the A source register (R 2 in the first example) • SB - specifies the B source register (R 3 in the first example and R 2 in the second example) Henry Hexmoor 31

ISA: Instruction Format (continued) 15 9 8 Opcode 6 5 Destination register (DR) 3 2 0 Source register A (SA) Operand (OP) (b) Immediate § This format supports instructions described by: • R 1 ← R 2 + 3 § The B Source Register field is replaced by an Operand field OP which specifies a constant. § The Operand: • 3 -bit constant • Values from 0 to 7 § The constant: • Zero-fill (on the left of) the Operand to form 16 -bit constant • 16 -bit representation for values 0 through 7 Henry Hexmoor 32

ISA: Instruction Format (continued) 15 9 8 Opcode 6 5 Address (AD) (Left) 3 2 0 Source reg- Address (AD) (Right) ister A (SA) (c) Jump and Branch § This instruction supports changes in the sequence of instruction execution by adding an extended, 6 -bit, signed 2 s-complement address offset to the PC value § The 6 -bit Address (AD) field replaces the DR and SB fields • Example: Suppose that a jump is specified by the Opcode and the PC contains 45 (0… 0101101) and Address contains – 12 (110100). Then the new PC value will be: 0… 0101101 + (1… 110100) = 0… 0100001 (45 + (– 12) = 33) § The SA field is retained to permit jumps and branches on N or Z based on the contents of Source register A Henry Hexmoor 33

ISA: Instruction Specifications § The specifications provide: • The name of the instruction • The instruction's opcode • A shorthand name for the opcode called a mnemonic • A specification for the instruction format • A register transfer description of the instruction, and • A listing of the status bits that are meaningful during an instruction's execution (not used in the architectures defined in this chapter) Henry Hexmoor 34

ISA: Instruction Specifications (continued) Instruction Speci fications for the Simple. Computer - Part 1 St atus Bits Instr uction Opcode Mnemonic Format Description Move A Increment Add Subtract D ecrement AND 00000001 00000101 0000110 0001001 0001010 0001011 MOVA INC ADD SUB DEC AND RD , RA R D, RA, RB R D, RA, RB R [DR] R[DR] R [DR] +1 + R[ SB] - R [SB] -1 Ù R[SB ] N, Z N, Z OR XOR RD, RA, RB R[DR] ¬ R[SA] Ú R[SB] RD, RA, RB R[DR] ¬ R[SA] Å R[SB] N, Z NO T R D, RA OR Exclusive OR NO T Henry Hexmoor ¬ R[SA ] ¬ R [SA] ¬ R[SA ] R[DR] ¬ R[SA ] 35 N, Z

ISA: Instruction Specifications (continued) Instruction Specifications for the Simple Computer - Part 2 Instr uction Opcode Mnemonic Format Description Move B Shift Right Shift Left Load Immediate Add Immediate Load Store Branch on Zero Branch on Negative Jump 0001100 0001101 0001110 1001100 1000010000 0100000 1100001 1110000 MOVB SHR SHL LDI ADI LD ST BRZ BRN JMP RD , RB RD, OP RD, RA, OP RD , RA RA, RB RA, AD RA R[DR] ¬ R[SB] R[DR] ¬ sr R[SB] R[DR] ¬ sl R[SB] R[DR] ¬ zf OP R[DR] ¬ R[SA] + zf OP R[DR] ¬ M[SA] ¬ R[SB] if (R[SA] = 0) PC ¬ PC + se AD if (R[SA] < 0) PC ¬ PC + se AD PC ¬ R[SA ] Henry Hexmoor 36 St atus Bits

ISA: Example Instructions and Data in Memory Repr esentation of Instructions and Data Deciimal Address Memory Contents Decimal Opcode Other Fields Operation 25 0000101 010 011 5 (Subtract) DR: 1, SA: 2, SB: 3 R 1 ¬ R 2 - R 3 35 0100000 100 101 32 (Store ) SA: 4, SB: 5 M[R 4] ¬ R 5 45 1000010 111 011 66 (Add Immediate) DR: 2, SA: 7, OP : 3 R 2 ¬ R 7 + 3 55 1100000 101 110 100 96 (Branch on Zero) AD: 44, SA: 6 If R 6 = 0, PC ¬ PC - 20 70 0000011000000 Data = 192. After execution of instruction in 35, Data = 80. Henry Hexmoor 37

Single-Cycle Hardwired Control 10 -8 § Based on the ISA defined, design a computer architecture to support the ISA § The architecture is to fetch and execute each instruction in a single clock cycle § The datapath from Figure 10 -11 will be used § The control unit will be defined as a part of the design § The block diagram is shown on the next slide Henry Hexmoor 38

V C N Z Extend Branch Control IR(8: 6) || IR(2: 0) PC Address Instruction memory Instruction P JB LBC IR(2: 0) RW DA AA Zero fill Instruction decoder D Register file A B BA Constant in 1 0 MUX B MB Address out Bus A D B A M F M R M P J B A A A B S D WW L B C CONTROL Figure 10 -15 FS V C N Z Bus B A Data out B Function unit Data in Address Data memory Data out F Data in Henry Hexmoor Bus D MW MD 39 0 1 MUX D DATAPATH

The Control Unit § The Data Memory has been attached to the Address Out and Data In lines of the Datapath. § The MW input to the Data Memory is the Memory Write signal from the Control Unit. § For convenience, the Instruction Memory, which is not usually a part of the Control Unit is shown within it. § The Instruction Memory address input is provided by the PC and its instruction output feeds the Instruction Decoder. § Zero-filled IR(2: 0) becomes Constant In § Extended IR(8: 6) || IR(2: 0) and Bus A are address inputs to the PC. § The PC is controlled by Branch Control logic Henry Hexmoor 40

PC Function (continued) § Branch Control determines the PC transfers based on five of its inputs defined as follows: • • N, Z – negative and zero status bits PL – load enable for the PC JB – Jump/Branch select: If JB = 1, Jump, else Branch BC – Branch Condition select: If BC = 1, branch for N = 1, else branch for Z = 1. § The above is summarize by the following table: PC Operation PL JB BC Count Up 0 X X Jump 1 1 X Branch on Negative (else Count Up) 1 0 1 Branch on Zero (else Count Up) 1 0 0 Henry Hexmoor 41

Instruction Decoder § The combinational instruction decoder converts the instruction into the signals necessary to control all parts of the computer during the single cycle execution § The input is the 16 -bit Instruction § The outputs are control signals: • Register file addresses DA, AA, and BA, • Function Unit Select FS • Multiplexer Select Controls MB and MD, • Register file and Data Memory Write Controls RW and MW, and • PC Controls PL, JB, and BC § The register file outputs are simply pass-through signals: DA = DR, AA = SA, and BA = SB Determination of the remaining signals is more complex. Henry Hexmoor 42

Instruction Decoder (continued) § The remaining control signals do not depend on the addresses, so must be a function of IR(13: 9) § Formulation requires examining relationships between the outputs and the opcodes… § Observe that for other than branches and jumps, FS = IR(12: 9) § This implies that the other control signals should depend as much as possible on IR(15: 13) (which actually were assigned with decoding in mind!) § To make some sense of this, we divide instructions into types as shown in the table on the next page Henry Hexmoor 43

Instruction Decoder (continued) Truth Table for Instruction Decoder Logic Instruction Bits Control Wo rd Bits Instruction Function Type 15 14 13 9 MB MD RW MW PL JB BC Function unit operations using registers 0 0 0 X 0 0 1 0 0 X X Memory read 0 0 1 X 0 1 1 0 0 X X Memory write 0 1 0 X X Function unit operations using register and constant 1 0 0 X X Conditional branch on zero (Z) 1 1 0 0 X X 0 0 1 0 0 Conditional branch on negative (N) 1 1 0 1 X X 0 0 1 Unconditional Jump 1 1 X X X 0 0 1 1 X Henry Hexmoor 1 44

Instruction Decoder (continued) § The types are based on the blocks controlled and the seven signals to be generated; types can be divided into two groups: • Datapath and Memory Control (First 4 types) • PC Control (Last 3 types) § In Datapath and Memory Control blocks controlled are considered: • Mux B (1 st and 4 th types) • Memory and Mux D (2 nd and 3 rd types) • By assigning codes with no or only one 1 for these, implementation of MB, MD, RW and MW are simplified. § In Control Unit more of a bit setting approach was used: • Bit 15 = Bit 14 = 1 were assigned to generate PL • Bit 13 values were assigned to generate JB. • Bit 9 was use as BC which contradicts FS = 0000 needed for branches. To force FS(6) to 0 for branches, Bit 9 into FS(6) is disabled by PL. § Also, useful bit correlations between values in the two groups were exploited in assigning the codes. Henry Hexmoor 45

Instruction Decoder (continued) § The end result by use of the types, careful assignment of codes, and use of don't cares, yields very simple logic: Instruction § This completes the Opcode DR SA SB 5– 3 2– 0 design of most of the 15 14 13 12 11 10 9 8– 6 essential parts of the single-cycle simple computer Henry Hexmoor 19– 17 16– 14 DA AA 13– 11 10 BA 9– 6 5 4 3 2 1 0 MB FS MD RW MW PL JB BC 46 Control word