Chapter 10 Boundary Scan and CoreBased Testing EE

Chapter 10 Boundary Scan and Core-Based Testing EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Outline q Introduction q Digital Boundary Scan (1149. 1) q Boundary Scan for Advanced Networks (1149. 6) q Embedded Core Test Standard (1500) q Comparison between 1149. 1 and 1500 EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Boundary Scan q Original objective: board-level digital testing q Now also apply to: § MCM and FPGA § Analog circuits and high-speed networks § Verification, debugging, clock control, power management, chip reconfiguration, etc. q History: § Mid-1980: JETAG § 1988: JTAG § 1990: First boundary scan standard – 1149. 1 EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Boundary Scan Family No. Main target Status 1149. 1 Digital chips and interconnects among chips Std. 1149. 1 -2001 1149. 2 Extended digital serial interface Discontinue 1149. 3 Direct access testability interface Discontinue 1149. 4 Mixed-signal test bus Std. 1149. 4 -1999 1149. 5 Standard module test and maintenance (MTM) bus Std. 1149. 5 -1995 (not endorsed by IEEE since 2003) 1149. 6 High-speed network interface Std. 1149. 6 -2003 EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Core-Based SOC Design EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Digital Boundary Scan – 1149. 1 q Basic concepts q Overall test architecture & operations q Hardware components q Instruction register & instruction set q Boundary scan description language q On-chip test support q Board/system-level control architectures EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Basic Idea of Boundary Scan EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

A Board Containing 4 IC’s with Boundary Scan EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

1149. 1 Boundary-Scan Architecture Internal Logic Boundary-Scan Register (consists of boundary Scan cells) 1 Test Data In (TDI) Internal Registers Bypass Register Test Data Out (TDO) Miscellaneous Register 1 Test Mode Select (TMS) Test Clock (TCK) Instruction Register TAP Controller 1 EE 141 VLSI Test Principles and Test Reset (TRST*) Ch. 10 -(optional) Boundary Scan and Core-Based 9 Testing - P. 9

Hardware Components of 1149. 1 q A test access port (TAP) consisting of : § 4 mandatory pins: Test data in (TDI), Test data out (TDO), Test mode select (TMS), Test clock (TCK), and § 1 optional pin: Test reset (TRST) A test access port controller (TAPC) q An instruction register (IR) q Several test data registers q § A boundary scan register (BSR) consisting of boundary scan cells (BSCs) § A bypass register (BR) § Some optional registers (Device-ID register, designspecified registers such as scan registers, LFSRs for BIST, etc. ) EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Basic Operations 1. Instruction sent (serially) through TDI into instruction register. 2. Selected test circuitry configured to respond to the instruction. 3. Test pattern shifted into selected data register and applied to logic to be tested 4. Test response captured into some data register 5. Captured response shifted out; new test pattern shifted in simultaneously 6. Steps 3 -5 repeated until all test patterns are Ch. 10 - Boundary Scan and Core-Based EE 141 VLSI Testapplied. Principles and Testing - P.

Boundary-Scan Circuitry in A Chip Data Register Design-Spec. Reg. Device-ID Reg. TDO TDI TRST* TMS TCK Boundary Scan Reg. T A P M U X 0 M U 1 D 1 X EN Bypass Reg. (1 -bit) T A P C 3 Clock. DR, Shift. DR, Update. DR Reset* Clock. IR, Shift. IR, Update. IR IR decode 3 Instruction Register Select EE 141 VLSI Test Principles and TCK Enable 12 Ch. 10 - Boundary Scan and Core-Based Testing - P. 12

Data registers Boundary scan register: consists of boundary scan cells q Bypass register: a one-bit register used to pass test signal from a chip when it is not involved in current test operation q Device-ID register: for the loading of product information (manufacturer, part number, version number, etc. ) q Other user-specified data registers (scan chains, LFSR for BIST, etc. ) q EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

A Typical Boundary-Scan Cell (BSC) q Operation modes § § EE 141 Normal: IN OUT (Mode = 0) Shift: TDI . . . IN OUT . . . TDO (Shift. DR = 1, Clock. DR) Capture: IN R 1, OUT driven by IN or R 2 (Shift. DR = 0, Clcok. DR) Update: R 1 OUT (Mode_Control = 1, Update. DR) VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

TAP Controller q. A finite state machine with 16 states q Input: TCK, TMS q Output: 9 or 10 signals included Clock. DR, Update. DR, Shift. DR, Clock. IR, Update. IR, Shift. IR, Select, Enable, TCK and TRST* (optional). EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

State Diagram of TAP Controller EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Main functions of TAP controller q Providing § § § EE 141 control signals to Reset BS circuitry Load instructions into instruction register Perform test capture operation Perform test update operation Shift test data in and out VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

States of TAP Controller q Test-Logic-Reset: normal mode q Run-Test/Idle: wait for internal test such as BIST q Select-DR-Scan: initiate a data-scan sequence q Capture-DR: load test data in parallel q Shift-DR: load test data in series q Exit 1 -DR: finish phase-1 shifting of data q Pause-DR: temporarily hold the scan operation (e. g. , allow the bus master to reload data) q Exit 2 -DR: finish phase-2 shifting of data q Update-DR: parallel load from associated shift registers Note: Controls for IR are similar to those for DR. EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Instruction Set q BYPASS § Bypass data through a chip q SAMPLE § Sample (capture) test data into BSR q PRELOAD § Shift-in test data and update BSR q EXTEST § Test interconnection between chips of board q EE 141 Optional § INTEST, RUNBIST, CLAMP, IDCODE, USERCODE, HIGH-Z, etc. Ch. 10 - Boundary Scan and Core-Based VLSI Test Principles and Testing - P.

Execution of BYPASS Instruction EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Execution of SAMPLE Instruction EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Execution of PRELOAD Instruction EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Execution of EXTEST Instruction (1/3) q Shift-DR EE 141 VLSI Test Principles and (Chip 1) 23 Ch. 10 - Boundary Scan and Core-Based Testing - P. 23

Execution of EXTEST Instruction (2/3) q Update-DR (Chip 1) q Capture-DR (Chip 2) EE 141 VLSI Test Principles and 24 Ch. 10 - Boundary Scan and Core-Based Testing - P. 24

Execution of EXTEST Instruction (3/3) q Shift-DR EE 141 VLSI Test Principles and (Chip 2) 25 Ch. 10 - Boundary Scan and Core-Based Testing - P. 25

Execution of INTEST Instruction (1/4) q Shift-DR EE 141 VLSI Test Principles and 26 Ch. 10 - Boundary Scan and Core-Based Testing - P. 26

Execution of INTEST Instruction (2/4) q Update-DR EE 141 VLSI Test Principles and 27 Ch. 10 - Boundary Scan and Core-Based Testing - P. 27

Execution of INTEST Instruction (3/4) q Capture-DR EE 141 VLSI Test Principles and 28 Ch. 10 - Boundary Scan and Core-Based Testing - P. 28

Execution of INTEST Instruction (4/4) q Shift-DR EE 141 VLSI Test Principles and 29 Ch. 10 - Boundary Scan and Core-Based Testing - P. 29

Boundary Scan Description Language (BSDL) q Now a part of IEEE 1149. 1 -2001 q Purposes: § Provide standard description language for BS devices. § Simplify design work for BS – automated synthesis is possible. § Promote consistency throughout ASIC designers, device manufacturers, foundries, test developers and ATE manufacturers. § Make it easy to incorporation BS into software tools for test generation, analysis and failure diagnosis. § Reduce possibility of human error when employing boundary scan in a design. EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Features of BSDL q Describes the testability features of BS devices that are compatible with 1149. 1. q S subset of VHDL. q System-logic and the 1149. 1 elements that are absolutely mandatory need not be specified. § Examples: BYPASS register, TAP controller, etc. q Commercial EE 141 VLSI Test Principles and tools to synthesize BSDL exist. Ch. 10 - Boundary Scan and Core-Based Testing - P.

Scan and BIST Support with Boundary Scan EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Bus Master for Chips with Boundary Scan (1/5) q Ring EE 141 architecture with shared TMS VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Bus Master for Chips with Boundary Scan (2/5) q Ring EE 141 architecture with separate TMS VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Bus Master for Chips with Boundary Scan (3/5) q Star EE 141 architecture VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Bus Master for Chips with Boundary Scan (4/5) q Multi-drop EE 141 VLSI Test Principles and architecture Ch. 10 - Boundary Scan and Core-Based Testing - P.

Bus Master for Chips with Boundary Scan (5/5) q Hierarchical EE 141 VLSI Test Principles and architecture Ch. 10 - Boundary Scan and Core-Based Testing - P.

Boundary scan for advanced networks – 1149. 6 q Rationale q Analog test receiver q Digital driver logic q Digital receiver logic q Test access port for 1149. 6 EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Rationale q Advanced signaling techniques are required for multiple-mega-per-second I/O. § Differential or AC-coupling networks q Coupling capacitor in AC-coupled networks blocks DC signals. q DC-level applied during EXTEST may decay to undefined logic level. EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Capturing AC-Coupled Signal with 1149. 1 EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

1149. 1 Configuration for Differential Signaling C C U TX EE 141 VLSI Test Principles and U RX Ch. 10 - Boundary Scan and Core-Based Testing - P.

Analog Test Receiver Response to AC and DC-Coupled Signals EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Digital Driver Logic EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Digital Receiver Logic EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

1149. 1 TAP – Driver Behavior During EXTEST_PULSE EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Embedded Core Test Standard - 1500 q SOC test problems q Overall architecture q Wrapper components and functions q Instruction set q Core test language q Core test supporting and system test configurations q Hierarchical test control and plug & play EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

SOC Test Problems/Requirements (1/2) q Mixing technologies: logic, processor, memory, analog § Need various DFT/BIST/other techniques q Deeply embedded cores § Need Test Access Mechanism q Hierarchical core reuse § Need hierarchical test management q Different core providers and SOC test developers § Need standard for test integration q IP protection/test reuse § Need core test standard/documentation EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

SOC Test Problems/Requirements (2/2) q Higher-performance core pins than SOC pins § Need on-chip, at-speed testing q External ATE inefficiency § Need “on-chip ATE” q Long test application time § Need parallel testing or test scheduling q Test power must be considered § Need lower power design or test scheduling q EE 141 Testable design automation § Need new testable design tools and flow VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

A System Overview of IEEE 1500 Standard EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Test Interface of A Core Wrapper EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Serial Test Circuitry of 1500 for a Core EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Wrapper Components q Wrapper series port (WSP) § Wrapper series input (WSI), Wrapper series output (WSO), Wrapper series control (WSC) q Wrapper parallel port (WPP) (optional) § Wrapper parallel input (WPI), Wrapper parallel output (WPO), wrapper parallel control (WPC) Wrapper instruction register (WIR) q Wrapper bypass regiester (WBY) q Wrapper data register (WBR) q § Consists of wrapper boundary cells (WBC’s) q EE 141 Core data register (CDR) (optional) Ch. 10 - Boundary Scan and Core-Based VLSI Test Principles and Testing - P.

Wrapper Series Control (WSC) signals q WRCK: wrapper clock terminal q AUXCKn: Optional auxiliary clocks, where n is the number of the clocks. q WRSTN: wrapper reset q Select. WIR: determine whether WIR is selected q Capture. WR: enable Capture operation q Shift. WR: enable Shift operation q Update. WR: enable Update operation q Transfer. DR: enable Transfer operation EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Wrapper Instruction Register EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Wrapper Boundary Register (WBR) q Consists of Wrapper boundary cells (WBC’s) q WBC § Terminals: Cell functional input (CFI), cell functional output (CFO), cell test input (CTI), cell test output (CTO) § Functional modes: Normal, inward facing, outward facing, nonhazardous (safe). § Operation events: Shift, capture, update, transfer, apply. EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Events of WBR (WBC) Shift: data advance one-bit forward on WBR’s shift path q Capture: data on CFI or CFO are captured and stored in WBC q Update: data stored in WBC’s shift path storage are loaded into an off-shift-path storage of the WBC q Transfer: move data to the storage closest to CTI or one bit closer to CTO q Apply: a derivative event inferred from other events to apply data to functional inputs of cores or functional outputs of WBR q EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Four Symbols Used in Bubble Diagrams for WBC’s Storage element EE 141 Data path VLSI Test Principles and Decision point Data paths from a source Ch. 10 - Boundary Scan and Core-Based Testing - P.

Some Typical WBC’s Represented by Bubble Diagrams EE 141 VLSI Test Principles and 58 Ch. 10 - Boundary Scan and Core-Based Testing - P. 58

Example 10. 1 - WIR Interface of WBY, WBR WDR(s) and CDR(s) EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Example 10. 2 - Schematic Diagram of WBC WC_SD 2_CIO EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

WS_BYPASS Instruction EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

WS_EXTEST Instruction EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

WP_EXTEXT Instruction EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

WS_SAFE Instruction EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

WS_PRELOAD Instruction EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

WP_PRELOAD Instruction EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

WS_CLAMP Instruction EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

WS_INTEST Instruction EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

WS_INTEST_SCAN Instruction EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

General Parallel TAM Structure EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Multiplexed TAM Architectures EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Daisy chained TAM Architecture EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Direct Access TAM Architectures EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Local Controller TAM Architectures EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Core Access Switch (CAS) Architecture EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Different Functional Modes of CAS EE 141 VLSI Test Principles and 76 Ch. 10 - Boundary Scan and Core-Based Testing - P. 76

Supporting Using CAS Structure EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

A Hierarchical Test Architecture Supporting Plug & Play Feature EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Detailed I/O and CTC of The Hierarchical Test Architecture EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

A Hierarchical Test Architecture with I/Os Compatible to 1149. 1 EE 141 VLSI Test Principles and Ch. 10 - Boundary Scan and Core-Based Testing - P.

Comparison between 1149. 1 and 1500 1149. 1 Purpose Board-level Parallel Mode No Extra Mandatory: TDI, Data/Control I/Os TDO, TMS, TCK Optional: TRST FSM Transfer Mode Latency between operations Mandatory Instructions EE 141 VLSI Test Principles and Yes No Yes 1500 Core-based Yes Mandatory: WSI, WSO, 6 WSC Optional: Transfer. DR, WPP, AUXCKn(s) No Yes No EXTEST, WS_EXTEST, BYPASS, WS_BYPASS, one Ch. 10 - Boundary Scan and Core-Based Testing - P. SAMPLE, Wx_INTEST,