Chapter 1 Performance Technology Trends Read Sections 1

Chapter 1 Performance & Technology Trends Read Sections 1. 5, 1. 6, and 1. 8

Section 1. 5: The Power Wall CPE 432 Chapter 1 — Computer Abstractions and Technology — 2

Power Trends n q Clock rates hit a “power wall” In CMOS IC technology × 30 CPE 432 Chapter 1. 3 5 V → 1 V × 1000 Chapter 1 — Computer Abstractions and Technology — 3

The power wall Performance was always improved by increasing frequency (up to 2004) n However by 2006, companies could not reduce generated power and remove more heat n Hence performance improvement could not be achieved by increasing frequency because of the increased power generated >>>>> THE POWER WALL n How else can we improve performance? n CPE 432 Chapter 1. 4 Chapter 1 — Computer Abstractions and Technology — 4

Read Section 1. 6: The Sea Change The Switch to Multiprocessors CPE 432 Chapter 1. 5 Chapter 1 — Computer Abstractions and Technology — 5

Uniprocessor Performance Uniprocessor performance is constrained by power, instructionlevel parallelism, memory latency CPE 432 Chapter 1. 6 Chapter 1 — Computer Abstractions and Technology — 6

A Sea Change is at Hand q The power challenge has forced a change in the design of microprocessors l q Since 2002 the rate of improvement in the response time of programs on desktop computers has slowed from a factor of 1. 5 per year to less than a factor of 1. 2 per year As of 2006 all desktop and server companies are shipping microprocessors with multiple processors – cores – per chip Product Cores per chip Clock rate Power q AMD Barcelona Intel Nehalem IBM Power 6 Sun Niagara 2 4 4 2 8 2. 5 GHz ~2. 5 GHz? 4. 7 GHz 1. 4 GHz 120 W ~100 W? 94 W Plan is to double the number of cores per chip per generation (about every two years) Plan not followed!! CPE 432 Chapter 1. 7 Dr. W. Abu-Sufah

Multicore microprocessors q Require explicitly parallel programming l In single core microprocessors, hardware implemented instruction level parallelism to execute multiple instructions IN PARALLEL l Instruction level parallelism is hidden from the programmer With the introduction of multicore microprocessors, The Free Lunch Era Ended !!! l Parallel programming is hard (harder) to do. Involves: - Programming for performance - Load balancing - Optimizing communication and synchronization CPE 432 Chapter 1. 8 Dr. W. Abu-Sufah 8

Read Section 1. 8: Pitfalls and Fallacies CPE 432 Chapter 1. 9 Dr. W. Abu-Sufah

Pitfalls and Fallacies q Pitfalls: Easily made mistakes q Fallacies: l Errors l Myths l… CPE 432 Chapter 1. 10 Dr. W. Abu-Sufah

n n Pitfall: Amdahl’s Law q Pitfall: Improving an aspect of a computer and expecting a proportional improvement in overall performance Example: multiply operations account for 80 seconds of a 100 seconds run time of a program How much improvement in multiply performance to get the program to run 5 times faster (i. e. in {100/5} = 20 s)? Can’t be done! CPE 432 Chapter 1. 11 Dr. W. Abu-Sufah

Amdahl’s Law Best Speedupoverall you could ever hope to do: fraction enhanced Ex. Timeold CPE 432 Chapter 1. 12 Ex. Timenew Dr. W. Abu-Sufah

Amdahl’s Law example n n New CPU 10 X faster I/O bound server, so 60% time waiting for I/O • Apparently, its human nature is to be attracted by 10 X faster, vs. keeping in perspective that it is just 1. 56 X faster CPE 432 Chapter 1. 13 13

Amdahl’s Law example: Make the common case fast n n Fraction = 0. 1, Speedup = 10 Fraction = 0. 9, Speedup = 10 CPE 432 Chapter 1. 14 14

Pitfall: MIPS as a Performance Metric n n MIPS: Millions of Instructions Per Second Doesn’t account for n n Differences in ISAs between computers Differences in complexity between instructions CPE 432 Chapter 1. 15 15

Pitfall: MIPS as a Performance Metric (cont. ) q How should MIPS be computed? l It is not the maximum theoretical MIPS quoted by the manufacturer. n CPI varies between programs on a given CPU CPE 432 Chapter 1. 16 Dr. W. Abu-Sufah