Chap 5 State Machine Design Chapter Design Objectives

Chap. 5: State Machine Design • Chapter Design Objectives – Manual state machine design • How to design state machines for complex synchronous sequential digital logic circuits – “Automatic” state machine design • How to convert algorithmic descriptions into HDL code that can be synthesized into working circuits • The general form of the circuit that will be synthesized from an algorithmic HDL description "Computer Design" by Sunggu Lee

State Machine Design • Used for systematic design of synchronous sequential digital logic circuits • Modification of FSM Method – FSM (Finite State Machine) method insufficient – FSM method only suitable for small sequential circuits with small numbers of external inputs • Allow more complicated checks for state transitions • Uses RTL statements within the states – Within one state, all RTL statements execute concurrently • Permits systematic conversion from algorithms to H/W • Variation of State Machine Method – Algorithmic State Machine (ASM) Method • Uses a graphical notation referred to as an ASM chart "Computer Design" by Sunggu Lee

Algorithms • Formal definition of an “algorithm” – A general step-by-step procedure for solving a problem that is CORRECT and TERMINATES. – A “proof” is required before a procedure can be called an algorithm. • Informal definition of an “algorithm” – A computer-program-like procedure for solving the problem given. • Algorithm description methods – Old (outdated) method: flowchart – Pseudocode: free-form procedural description "Computer Design" by Sunggu Lee

Structure of General Digital Circuit "Computer Design" by Sunggu Lee

Partitioning of Digital Circuits • Control Logic Section – logic required to generate control signals for registers, adders, counters, etc. • Datapath Section – all logic not included in the control logic section • registers, adders, counters, multiplexers, etc. – typically the “word”-sized data manipulation and storage components through which the data “flows” "Computer Design" by Sunggu Lee

Example Layout for a Chip input data control and status signals datapath elements 10/6/2020 "Computer Design" by Sunggu Lee output data 6

Manual State Machine Method • (1) Pseudocode – create an algorithm to describe desired circuit operation • (2) RTL Program – convert the pseudocode into an RTL Program (HDL or ASM chart format) • (3) Datapath – design the datapath based on the RTL Program • (4) State Diagram – based on the RTL Program and datapath • (5) Control Logic Design "Computer Design" by Sunggu Lee

RTL Program • HDL Format – Like a pseudocode description, except that each “step” is one state of the state machine • All operations within one state execute concurrently – All operations are RTL operations • ASM Chart Format – Uses a graphical notation that resembles a flowchart – Main difference • All operations within one state execute concurrently "Computer Design" by Sunggu Lee

ASM Charts • Consists of 3 types of constructs Example ASM Chart – State object RTL Statements – Condition object condition How could we replace this with a conditional output object? Is there any difference in operation? – Conditional output object RTL statements 10/6/2020 "Computer Design" by Sunggu Lee 9

Manual State Machine Design Example: Coin Changer Circuit • Problem: Design a “coin changer” circuit that changes 1000 Won notes to 100 Won coins. • Example usage: – the coin changers used in electronic game arcades. 10/6/2020 "Computer Design" by Sunggu Lee 10

Step 1: Pseudocode • (1) Initialize COIN_OUT to 0 • while (TRUE) do – (2) REJECT 0 – (3) Wait until MONEY_INPUT – (4) If (not MONEY_VALID) then • REJECT 1; • Go to Step (2); – (5) For i = 0 to 9 do • COIN_OUT 1; • COIN_OUT 0; • endwhile "Computer Design" by Sunggu Lee

Step 2: RTL Program (HDL Format) • • (0) COIN_OUT 0; while (TRUE) do Each “step” corresponds to a “state” in the control logic. The RTL operations within a single “state” are executed concurrently. (1) REJECT 0; If (MONEY_INPUT == 0) then go to Step (1); else if (MONEY_VALID == 0) then (2) REJECT 1; else (3) COUNT 0; (4) COIN_OUT 1; COUNT + 1; (5) COIN_OUT 0; if (COUNT < 9) then /* concurrent with above statement */ go to Step (6); endwhile; "Computer Design" by Sunggu Lee

Step 2: RTL Program (ASM Chart) "Computer Design" by Sunggu Lee

Step 3: Datapath "Computer Design" by Sunggu Lee

Step 4: State Diagram "Computer Design" by Sunggu Lee

Step 5: Control Logic Example of one-hot control logic design method (refer to pp. 18 -19 of this ppt file) "Computer Design" by Sunggu Lee

Control Logic Design Methods • One-FF-per-state method – also referred to as “one-hot” or “delay element” method – uses one FF for each state of the state machine • PLD-based method – uses encoded states • number of FFs used = integer_part (log (number_of_states)) – results in the most compact implementation • Sequence-counter method – for use with cyclical state transition patterns • e. g. , a CPU with equal numbers of states for each instruction – outputs of the “counter” are the control logic “states” "Computer Design" by Sunggu Lee

One-FF-Per-State Method • Uses one-to-one transformations from state diagram to digital logic components – Also applicable to ASM charts • Transformations – state in state diagram • transforms to a D flip-flop – transition from one state to another in state diagram • transforms to a path from the Q or Q’ output of one state flip-flop to the D input another D flip-flop – labeled transition in state diagram • AND gate with the labeled condition • labeled (conditional) signal activation also leads to AND gate – Several transitions into a single state • OR gate with one input for each transition "Computer Design" by Sunggu Lee

One-Hot Transformation Example "Computer Design" by Sunggu Lee

PLD-Based Control Logic Example Next State Variables Current conditions State (status signals) Variables control signal outputs Contains programmed logic to implement next state and output logic equations 10/6/2020 "Computer Design" by Sunggu Lee 20

PLD-Based Implementation (Using an EPROM as a PLD) A 14 10/6/2020 "Computer Design" by Sunggu Lee 21

A 14 10/6/2020 "Computer Design" by Sunggu Lee 22

Overall Manual State Machine Design Approach • Write down a pseudocode solution – test it out using a short computer program • Convert the pseudocode to an RTL program – try to “optimize” ASM chart, so it uses a small number of states – can use HDL format or ASM chart format • Derive the datapath from the RTL program – figure out the datapath components and signals needed • Form a state diagram with states and control signal activations • Derive the control logic design – one-hot or PLD-based approach "Computer Design" by Sunggu Lee

Automatic State Machine Design • Describe the desired circuit using pseudocode • Convert the pseudocode into an HDL program – If the pseudocode is converted into an ASM chart, then a conversion tool (e. g. , the Exsedia Nimbus tool) can be used to automatically convert an ASM chart into synthesizable Verilog or VHDL code. • Use a synthesis tool to convert the HDL code into a working hardware circuit – Implement for the target hardware architecture "Computer Design" by Sunggu Lee

Recommended Pseudocode Format • (0) initialize variables while (true) do (1) first step of algorithm (2) second step of algorithm. . . (k) for (i = 0; i < max; i++) …. . . (m) function call … (n) n’th step of algorithm endwhile "Computer Design" by Sunggu Lee

Corresponding Synthesizable Verilog Code • always @(negedge reset_n or posedge clk) begin if (~reset_n) begin state <= 0; (other initialization operations) end else begin // on posedge clk state <= state + 1; // auto-increment state case (state) begin 0: begin // first step of algorithm end 1: … // second step of algorithm 2: begin ret_state <= 3; state <= `FUNCTION_1; end 3: … `FUNCTION_1: … // 1 st step of function … `FUNCTION_1+k: state <= ret_state; // return from function default: $display(“Unknown state”); endcase end // of else (posedge clk) end // of always "Computer Design" by Sunggu Lee

Conversion of For Loops • Conversion of: for (i = 0; i < max; i++) … endfor • Options – Use same sequence of operations • i = 0; • while (i < max) i = i + 1; . . . Endwhile – Decrement the count instead of incrementing I • count = max; • repeat count = count – 1; . . . until (count == 0); – Other equivalent series of operations also possible "Computer Design" by Sunggu Lee

Use of Code Templates • Use the code in pp. 178 -179 as a template for the creation of new Verilog programs • Typical pseudocode operations used and corresponding HDL code – Table 5. 2 (p. 178) – For loops – discussed on previous page "Computer Design" by Sunggu Lee

Textbook Examples • Manual state machine design – Factorial circuit – Vending machine • Automatic (synthesis-based) state machine design – Vending machine • Correspondence to manual solution shown – LCD controller "Computer Design" by Sunggu Lee

Example: Two-Phase Handshake Transmitter Circuit • Used to communicate between two circuits in different clock domains (i. e. , clocked by different clock signals) – In large or high-performance circuits, different circuits (or subcircuits) will use different clock inputs because of clock synchronization difficulties or simply because they are independent circuits – Communication of data packets between such circuits requires a handshaking protocol • Solution implemented using the automatic synthesis-based method instead of the manual state machine design method used in Example 5. 2 10/6/2020 "Computer Design" by Sunggu Lee 30

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Pseudocode 1. req 0; while (TRUE) do 2. wait until (ready = 1); // data ready 3. data_to_be_sent; 4. req not req; // invert req value 5. wait until (ack = req); end while; "Computer Design" by Sunggu Lee

Synthesizable Verilog Code • always @(negedge reset_n or posedge clk) begin if (~reset_n) begin req <= 0; state <= 0; // state should be a 2 -bit reg signal end else begin // on posedge clk state <= state + 1; // auto-increment current state case (state) begin 0: if (~ready) state <= 0; // repeat until ready 1: data <= data_in; // assume data_in is data to be sent 2: req <= ~req; // send request signal 3: if (ack != req) state <= 2; // stay in this state until (ack == req) default: $display(“Error: Unknown state”); endcase end // of else (posedge clk) end // of always "Computer Design" by Sunggu Lee