Changing Paradigms FastTurn RF and MixedSignal IP IEEE
- Slides: 9
Changing Paradigms Fast-Turn RF and Mixed-Signal IP IEEE Annual EDP-2001 Workshop session on Analog/MS Design Flows James Spoto Enablix Solutions April 10, 2001
Communications Systems Challenge Today, the wireless & optical Industry is limited in ability to deliver timely RF & mixed signal based products n n n Scarce skill set No standard/commercial design platforms & IP Long custom development cycle with many spins Expensive (people, non-reuse, lab) Not available (until now!) in pure-play foundries RF and mixed signal design cycles are pacing wireless & optical product Time-to-Market 12/16/2021 2
IP Hierarchy RF/Mixed-Signal Digital CDMA/GSM/TDMA MS BB CDMA/GSM/TDMA Radios Ethernet/ADSL/Cable Phys CDMA/GSM/TDMA Dig BB Bluetooth/802. 11 a, b BB Ethernet/ADSL/CBL data pumps and controllers Costly, Risky, Lengthy Custom Design No Significant Commercial Suppliers Differentiating IP ARM/MIPS/DSP cores Enabling IP & Datapath/Memory Compilers Design Platform Cell Libs/design platforms Semi Foundries Growing List of Commercial Suppliers 12/16/2021 RF/Mixed-Signal Subsystems Driving Costs and Schedules 3
RF/Mixed-Signal R&D Investment Total R&D Investment is 15% to 20% of IC Shipments % of Total CDMA/GSM/TDMA MS BB CDMA/GSM/TDMA Radios Ethernet/ADSL/Cable Phys 50% 25% A/Ds, RF Transceivers, PLLs Filters, Amps, Mixers, VCOs, S/Hs 25% Design Platform (Tools, Lib, Flow) Differentiating IP Enabling IP & Design Platform Semi Foundries Design platforms and Enabling IP make up over 50% of R&D costs 12/16/2021 4
Design Platform Architecture RF/MS Methodology & Flow IC Product Specification Design Capture Exploration, Optimization & Synthesis & Simulation Physical Design Final Design Verification Finished Product Tape-out Platform IP Component Representations Symbols & Spice Models Device Component Interconnect & Generators & LVS, DRC, Ext Tech Files Descriptions. Device Parasitics. Layout Options Schematic Capture 12/16/2021 Circuit DRC, LVS & Analog P&R Simulatio Extraction & Layout n& Tools Editor Waveform Tool Leading EDA Tools Industry 5
Complex Generators - Differential Inductor Parameterized Design Input Equivalent Circuit Model - Automatically Generated Layout - Automatically Generated 12/16/2021 6
Package Models 12/16/2021 7
Portable and Configurable IP Components Created in days vs months! Parameterized Device Generators Specifications OK Cancel Apply Help Selection----------------------------Application Cell Topology Technology Speed #Bits R D A C Specification--------------------------Gain Slew Rate Input Swing Noise PSRR Bandwidth Settling Time Output Swing Power CMRR Performance---------------------------AC Transient Noise PSRR Swing SAR Out CDAC Vref Input Disto w=f 1(gain, bw, sr…) l=f 2(gain, bw, sr…) Mapping Modules Gain = F(Speed, #bits) BW = F(Speed, #bits) SR = F(speed, #bits) Floorplan Tiler Foundry Specific Technology Data 12/16/2021 Device level P&R, Compaction 8
Generated PLL* Spec 2 Weeks Multi-Phase PLL TSMC 0. 25 um 25 MHz-165 MHz Application - Digital Video GDSII Data Sheet Simulations Models LVS Netlist *Courtesy and Copyright Portability, Inc. © 2001. All rights reserved 12/16/2021 9
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