Challenges and advantages making analog frontends for Silicon

Challenges and advantages making analog front-ends (for Silicon Strip Detectors) in deep submicron technologies Jan Kaplon Challenges and advantages making analog front-ends in deep submicron technologies 1

Outline q q q General requirements for silicon strip detectors electronics Technology scaling and its consequences Improving the open loop gain of amplifier stages q Motivations q Methods Biasing in weak inversion as a solution for input stage q Motivations q Costs Comparison between front end amplifiers designed for short strip (5 to 10 p. F detector capacitance) in 250 and 130(90)nm process q Architecture q Performance Challenges and advantages making analog front-ends in deep submicron technologies 2

General requirements for the Front-End tracker electronics for SLHC detectors q q q q Detector capacitance in the order of p. F Low power (<1 m. W/channel), low noise (S/N>15 ENC < 1500 e-) (optimization of power for a minimum affordable noise level) Collisions of particles every 25 ns data time tagging to the given BCO (peaking times <25 ns) Low input impedance efficient charge collection and low cross talk signals Stability required phase margin above 85 to 90 degree Optimum PSRR (large systems, difficult to provide clean power supply) Radiation hardness – doses >2× 1014 N/cm 2 (1 Me. V) and >10 MRad (CMOS front end preferred) Challenges and advantages making analog front-ends in deep submicron technologies 3

CMOS technology scaling q q q Technology scaling ; formerly proportional reduction of all transistor features size (tox, L, W) scaled together with voltage supply and vt threshold voltage (constant field scaling). Smaller feature size higher integration scale, lower power consumption/higher speed etc. Constant field scaling required proportional scaling of threshold voltage this is limited by subthreshold slope of the MOS transistor (limit for minimum Vt >200 m. V) Scaling today ; constant voltage scaling introducing short channel effects q mobility reduction(vertical and longitudinal field) q degradation of output conductance (channel length modulation, Drain Induced Barrier Lowering (decreasing of Vt for higher Vds)) Challenges and advantages making analog front-ends in deep submicron technologies 4

Comparison of basic analogue parameters for three generations of IBM CMOS processes IBM CMOS 250 nm RF 130 nm RF 90 nm LP (low power) t. OX physical/effective 5 nm/6. 2 nm 2. 2 nm/3. 12 nm 2. 1 nm/2. 8 nm Ka (COX∙µ) NMOS 330 u. A/V 2 720 u. A/V 2 800 u. A/V 2 Vdd 2. 5 V 1. 2 V (1. 5 V) 1. 2 V gm/gds Weak Inv. 70 30 18 Peak ft 35 GHz 94 GHz 105 GHz Scaling advantages; higher ft, higher Ka Challenges for front end; lower Vdd (lower dynamic range), lower intrinsic transistor gain Challenges and advantages making analog front-ends in deep submicron technologies 5

Motivations to increase open loop gain q Lowering input impedance of preamplifier q Better charge collection efficiency q Lower cross talk q PSRR (all single ended stages) Challenges and advantages making analog front-ends in deep submicron technologies 6

Charge collection from silicon strip detectors, cross talk signals Optimal open loop gain preamplifier designed for 5 to 20 p. F detector capacitance is around 70 to 80 d. B (in order to provide cross talk less than 5%) Challenges and advantages making analog front-ends in deep submicron technologies 7

Motivations to increase open loop gain q Lowering input impedance of preamplifier q Lower cross talk q Better charge collection efficiency q PSRR (all single ended stages) Challenges and advantages making analog front-ends in deep submicron technologies 8

PSRR for single ended stage (1) Challenges and advantages making analog front-ends in deep submicron technologies 9

PSRR for single ended stage (2) Loop gain Driving KU improves PSRR. All single ended stages should be designed as feedback amplifiers with high open loop gain. Challenges and advantages making analog front-ends in deep submicron technologies 10

PSRR for single ended stage (3) Power supply disturbance (1 V) seen at cascode output working in open loop configuration (red) and in transimpedance preamplifier (blue). 130 nm version of front end. Challenges and advantages making analog front-ends in deep submicron technologies 11

Basic configurations for gain boosting Intrinsic gain in 250 nm ~70 V/V we need 70 to 80 d. B (2000 to 10000 V/V)… Challenges and advantages making analog front-ends in deep submicron technologies 12

Cascade q Two stage i. e. two pole circuit; needs to be stabilized q Significant gain after first stage; Miller effect in case of driving from high impedance (as for silicon detector) not used as an preamplifier stage q PSRR defined by gain of first stage only q In 90 nm the gain of cascade is significantly degraded because of intrinsic transistor gain, some circuits which works in 250 nm version shows bad PSRR characteristic Challenges and advantages making analog front-ends in deep submicron technologies 13

Cascode; common source – common gate amplifier q single stage amplifier; one dominant pole q good PSRR q no Miller effect (low gain of common source stage) q If cascode load RL very high the overall gain KU comparable with cascade Challenges and advantages making analog front-ends in deep submicron technologies 14

Regulated cascode q Cascode transistor controlled with common source amplifier q Higher output conductance of cascode; possible higher gain q GBW the same as for simple cascode Challenges and advantages making analog front-ends in deep submicron technologies 15

Boosting bandwidth and gain in cascode q Extra current source to drain of M 1 increase of gm 1 q Direct impact on gain bandwidth q Gain changed according to output conductance of cascode and active load Challenges and advantages making analog front-ends in deep submicron technologies 16

Active load for cascode stage (cascode load) q Amplification of r. DS 1 by gm 2 q For our application; OK for 250 nm, not sufficient for 130 & 90 nm Challenges and advantages making analog front-ends in deep submicron technologies 17

Active load for cascode stage (regulated cascode load) q Amplification of r. DS 1 by gm 2 and gm 3 q Used in 130 & 90 nm versions of preamplifiers Challenges and advantages making analog front-ends in deep submicron technologies 18

Biasing of the cascode q All, four, transistors must be in the saturation (VDS ≥ VGS – VT) q Technology scaling Vdd diminished from 2. 5 V in 250 nm to 1. 2 V in 130 nm and 90 nm CMOS possible problems with dynamic range q Solution subthreshold operation (VGS ≈ VT) q Minimum VDS SAT for weak inversion roughly 5 UT (125 m. V) Challenges and advantages making analog front-ends in deep submicron technologies 19

Biasing transistors in weak inversion; some consequences Challenges and advantages making analog front-ends in deep submicron technologies 20

Impact of the inversion order on the speed of CMOS circuit Transit frequency ft as a function of inversion order for 250 nm CMOS technology * For devices biased in weak inversion we never obtain highest possible speed of a given technology * C. Enz, “MOS transistor modeling for RF IC design”, IEEE J. Solid-State Circ. , vol. 35, no. 2, pp. 186 -201) Challenges and advantages making analog front-ends in deep submicron technologies 21

Noise of the active load (1) If all transistor in weak inversion the gm is defined only by current all gm the same Increase of input series noise by ~40%! Challenges and advantages making analog front-ends in deep submicron technologies 22

Noise of the active load (2) Resistive degeneration of gm works But we have to spend another ~100 m. V taken out from Vdd… Challenges and advantages making analog front-ends in deep submicron technologies 23

Noise optimization in CR-RCn filters for multi-channel FE electronics (remainder) CR-RC 2 CR-RC 3 FV 0. 96 0. 92 0. 97 Fi 0. 96 0. 8 0. 72 series parallel AFP Resistive feedback Challenges and advantages making analog front-ends in deep submicron technologies 24

Transconductance in MOS transistor (EKV) Specific current WI/SI interpolation for If=ID/IS Transconductance: gm in weak inversion IBM 130 nm NMOS L=300 nm q Weak inversion provides highest transconductance at a given bias current q Some technologies report excess noise for devices in strong inversion q Conclusion; weak inversion in input transistor is good from the standpoint of power consumption/noise optimization Challenges and advantages making analog front-ends in deep submicron technologies 25

Comparison of architectures and performances of front ends implemented in 250, 130 & 90 nm processes Challenges and advantages making analog front-ends in deep submicron technologies 26

Front end channel in IBM 250 nm (ABCN 250) 6 m. V/f. C tp 13 ns 36 m. V/f. C tp 18 ns 100 m. V/f. C tp 22 ns Challenges and advantages making analog front-ends in deep submicron technologies 27

Front end channel in 130 nm & 90 nm technology (SCT short strips) 5. 5 m. V/f. C tp 8 ns 30 m. V/f. C tp 18 ns 100 m. V/f. C tp 22 ns Challenges and advantages making analog front-ends in deep submicron technologies 28

Preamplifiers open loop gain 90 nm, 70 d. B, GBW=3. 5 GHz Iin=80 u. A 130 nm, 80 d. B, GBW=2 GHz Iin=80 u. A 250 nm, 85 d. B, GBW=1. 2 GHz Iin=140 u. A Challenges and advantages making analog front-ends in deep submicron technologies 29

Preamplifiers input impedances 250 nm, 85 d. B, 330Ω @ 25 MHz Iin=140 u. A 130 nm, 330Ω @25 MHz Iin=80 u. A In all cases the cross talk signals less than 3% Detector 1. 5 p. F to bulk + 2 x 1. 6 p. F to neighbor 90 nm, 380Ω @25 m. Hz Iin=80 u. A Challenges and advantages making analog front-ends in deep submicron technologies 30

PSRR * 1/PSRR 250 nm, -3 d. B @ 25 MHz Iin=140 u. A, Cin=5 p. F to GND 130 nm, -0. 5 d. B @ 25 MHz Iin=80 u. A, Cin=5 p. F to GND PSRR defined as the ratio of the 1 V signal at the power supply line to the signal at the output. For two different front end one should also look at the charge gain! * 90 nm, +0. 5 d. B @ 25 MHz Iin=80 u. A, Cin=5 p. F to GND Challenges and advantages making analog front-ends in deep submicron technologies 31

PSRR (2) PSRR improves when: q Cin decreases (also in case of real detector when part of the detector capacitance is connected to neighboring channel) q Bias current increases (GBW increases loop gain increases) Challenges and advantages making analog front-ends in deep submicron technologies 32

Phase margin 90 nm 130 nm We want to have 90 degree for nominal input capacitance (5 p. F), this has impact on input impedance and PSRR but safety first. Challenges and advantages making analog front-ends in deep submicron technologies 33

Linearity and dynamic range In 250 nm version the dynamic range (limit in discriminator stage - might be adjusted) is about 12 f. C In 130 nm and 90 nm version linear range up to 6 f. C Difference caused by Vdd (2. 5 V in 250 nm, 1. 2 V in 130 nm and 90 nm versions) Challenges and advantages making analog front-ends in deep submicron technologies 34

Comparison of power consumption at constant ENC Comparison of power consumption done for Cdetector = 5 p. F, Ileakage=600 n. A and ENC = 800 e 250 nm 130 nm 90 nm Iinput 140 u. A 100 u. A Itotal 280 u. A 180 u. A Vdd 2. 5 V (2. 2 V) 1. 2 V Challenges and advantages making analog front-ends in deep submicron technologies 35

Conclusion q q q Big improvement in noise/power performance from 250 nm to 130 and 90 nm versions Some improvements in AC characteristics due to higher bandwidth in newer technologies (better PSRR and input impedance). Differences in between 130 nm and 90 nm almost negligible. 90 nm shows higher bandwidth but lower gain than 130 nm. This has slight impact on differences between input impedance, PSRR and phase margin. Dynamic range in 90 nm and 130 nm lower than in 250 nm but still sufficient for tracking applications (6 f. C range with gain of 100 m. V/f. C) For 130 nm and 90 nm front end amplifiers we need 1. 2 V which is a nominal Vdd for those technologies. It means that the input voltage for on chip LDO must be higher than nominal. Improvements between 250 nm and 130/90 nm in terms of noise/power performance due to: q Excess noise in 250 nm (in the order of 30%) q Better transconductance parameter in 130/90 nm q Higher ft (less power in buffer/shaper/discriminator stages) Challenges and advantages making analog front-ends in deep submicron technologies 36

Addendum Challenges and advantages making analog front-ends in deep submicron technologies 37

Principles of the silicon detectors for tracking applications q q q p-n junction reverse biased forms the detection zone Ionization along the track of the high-energy particle For 300µm Si detector the most probable signal is around 3. 5 f. C (non-irradiated detector) Electric field proportional to bias provides drifting of the created charge – induced current is readout by the Front-End electronics Spatial resolution provided by the segmentation of the detector Challenges and advantages making analog front-ends in deep submicron technologies 38

Reception of signals from silicon detector – basic configuration of the preamplifier q Charge sensitive preamplifier q q q Delta-Dirac current pulses integrated on feedback capacitance Discharge provided by the feedback resistor (prevents saturation) Mode of the preamplifier is defined by feedback time constant τF=RF×CF q q τF comparable with the time constant of the shaper transimpedance preamplifier τF >> time constant of the shaper charge amplifier Challenges and advantages making analog front-ends in deep submicron technologies 39

Input impedance and cross-talk signals for charge and transimpedance amplifiers q Input impedance and cross-talk for amplifier with 83 d. B gain and 800 MHz Gain Bandwidth Product (GBP) working in charge and transimpedance configuration Challenges and advantages making analog front-ends in deep submicron technologies 40

Influence of GBP on preamplifier input impedance and cross-talk signals q 2 lower Gain-Bandwidth Product 2 higher input impedance and cross-talk signals Challenges and advantages making analog front-ends in deep submicron technologies 41

Noise sources in MOS transistor q Noise spectra densities of the elementary noise sources: Channel thermal noise Gate Induced Current noise (GIC): Channel thermal GIC noise correlation Flicker (1/f) noise Challenges and advantages making analog front-ends in deep submicron technologies 42

Noise filtering in multi-channel FE electronics q q q CR-RCn continuous filters – simplicity and performance (1 high-pass + n low-pass stages) ENC – Equivalent Noise Charge: Output Noise / Pulse Gain tpeak defined by timing requirements, Cd defined by experiment ENC optimised by controlling the series and parallel noise sources choice of the optimal input device Challenges and advantages making analog front-ends in deep submicron technologies 43

Noise optimization of the input transistor ENC series noise contribution of the input transistor as a function of device dimensions (IBM 130 nm, input transistor NMOS L=300 nm, detector capacitance 10 p. F ) Challenges and advantages making analog front-ends in deep submicron technologies 44