Central Processing Unit 1 CENTRAL PROCESSING UNIT Introduction

Central Processing Unit 1 CENTRAL PROCESSING UNIT • Introduction • General Register Organization • Stack Organization • Instruction Formats • Addressing Modes • Data Transfer and Manipulation • Program Control • Reduced Instruction Set Computer Organization Computer Architectures Lab

Central Processing Unit Introduction 2 MAJOR COMPONENTS OF CPU Storage Components Registers Flags Execution(Processing) Components Arithmetic Logic Unit(ALU) Arithmetic calculations, Logical computations, Shifts/Rotates Transfer Components Bus Control Components Control Unit Register File ALU Control Unit Computer Organization Computer Architectures Lab

Central Processing Unit General Register Organization 3 GENERAL REGISTER ORGANIZATION Input Clock R 1 R 2 R 3 R 4 R 5 R 6 R 7 Load (7 lines) SELA { 3 x 8 decoder MUX A bus SELD OPR } SELB B bus ALU Output Computer Organization Computer Architectures Lab

Central Processing Unit Control 4 OPERATION OF CONTROL UNIT The control unit Directs the information flow through ALU by - Selecting various Components in the system - Selecting the Function of ALU Example: R 1 <- R 2 + R 3 [1] MUX A selector (SELA): BUS A R 2 [2] MUX B selector (SELB): BUS B R 3 [3] ALU operation selector (OPR): ALU to ADD [4] Decoder destination selector (SELD): R 1 Out Bus Control Word 3 SELA 3 SELB 3 SELD 5 OPR Encoding of register selection fields Binary Code 000 001 010 011 100 101 110 111 Computer Organization SELA Input R 1 R 2 R 3 R 4 R 5 R 6 R 7 SELB Input R 1 R 2 R 3 R 4 R 5 R 6 R 7 SELD None R 1 R 2 R 3 R 4 R 5 R 6 R 7 Computer Architectures Lab

Central Processing Unit Control 5 ALU CONTROL Encoding of ALU operations OPR Select 000001 000101 00110 01000 01010 01100 01110 10000 11000 Operation Transfer A Increment A ADD A + B Subtract A - B Decrement A AND A and B OR A and B XOR A and B Complement A Shift right A Shift left A Symbol TSFA INCA ADD SUB DECA AND OR XOR COMA SHRA SHLA Examples of ALU Microoperations Symbolic Designation Microoperation R 1 R 2 - R 3 R 4 R 5 R 6 + 1 R 7 R 1 Output R 2 Output Input R 4 shl R 4 R 5 0 Computer Organization SELA SELB R 2 R 3 R 4 R 6 R 1 R 2 Input R 4 R 5 R 5 SELD OPR R 1 SUB R 4 OR R 6 INCA R 7 TSFA None TSFA R 4 SHLA R 5 XOR Control Word 010 011 00101 100 110 001 010 000 101 101 000 000 000 101 100 111 000 100 101 01010 00001 00000 11000 01100 Computer Architectures Lab

Central Processing Unit Stack Organization 6 REGISTER STACK ORGANIZATION Stack - Very useful feature for nested subroutines, nested loops control - Also efficient for arithmetic expression evaluation - Storage which can be accessed in LIFO - Pointer: SP - Only PUSH and POP operations are applicable stack Register Stack 63 Flags FULL Address EMPTY Stack pointer SP Push, Pop operations C B A 4 3 2 1 0 DR /* Initially, SP = 0, EMPTY = 1, FULL = 0 */ PUSH SP + 1 M[SP] DR If (SP = 0) then (FULL 1) EMPTY 0 Computer Organization POP DR M[SP] SP - 1 If (SP = 0) then (EMPTY 1) FULL 0 Computer Architectures Lab

Central Processing Unit Stack Organization 7 MEMORY STACK ORGANIZATION 1000 Memory with Program, Data, and Stack Segments PC Program (instructions) AR Data (operands) SP - A portion of memory is used as a stack with a processor register as a stack pointer - PUSH: - POP: 3000 stack 3997 3998 3999 4000 4001 DR SP - 1 M[SP] DR DR M[SP] SP + 1 - Most computers do not provide hardware to check stack overflow (full stack) or underflow(empty stack) Computer Organization Computer Architectures Lab

Central Processing Unit Stack Organization 8 REVERSE POLISH NOTATION Arithmetic Expressions: A + B Infix notation + A B Prefix or Polish notation A B + Postfix or reverse Polish notation - The reverse Polish notation is very suitable for stack manipulation Evaluation of Arithmetic Expressions Any arithmetic expression can be expressed in parenthesis-free Polish notation, including reverse Polish notation (3 * 4) + (5 * 6) 3 4 3 12 5 12 3 4 * 5 Computer Organization 34*56*+ 6 5 12 30 12 42 6 * + Computer Architectures Lab

Central Processing Unit 9 Instruction Format INSTRUCTION FORMAT Instruction Fields OP-code field - specifies the operation to be performed Address field - designates memory address(es) or a processor register(s) Mode field - specifies the way the operand or the effective address is determined The number of address fields in the instruction format depends on the internal organization of CPU - The three most common CPU organizations: Single accumulator organization: ADD X /* AC + M[X] */ General register organization: ADD R 1, R 2, R 3 /* R 1 R 2 + R 3 */ ADD R 1, R 2 /* R 1 + R 2 */ MOV R 1, R 2 /* R 1 R 2 */ ADD R 1, X /* R 1 + M[X] */ Stack organization: PUSH X /* TOS M[X] */ ADD Computer Organization Computer Architectures Lab

Central Processing Unit Instruction Format 10 THREE, AND TWO-ADDRESS INSTRUCTIONS Three-Address Instructions Program to evaluate X = (A + B) * (C + D) : ADD R 1, A, B /* R 1 M[A] + M[B] ADD R 2, C, D /* R 2 M[C] + M[D] MUL X, R 1, R 2 /* M[X] R 1 * R 2 */ */ */ - Results in short programs - Instruction becomes long (many bits) Two-Address Instructions Program to evaluate X = (A + B) * (C + D) : MOV ADD MUL MOV Computer Organization R 1, A R 1, B R 2, C R 2, D R 1, R 2 X, R 1 /* R 1 M[A] /* R 1 + M[A] /* R 2 M[C] /* R 2 + M[D] /* R 1 * R 2 /* M[X] R 1 */ */ */ Computer Architectures Lab

Central Processing Unit Instruction Format 11 ONE, AND ZERO-ADDRESS INSTRUCTIONS One-Address Instructions - Use an implied AC register for all data manipulation - Program to evaluate X = (A + B) * (C + D) : LOAD A /* AC M[A] */ ADD B /* AC + M[B] */ STORE T /* M[T] AC */ LOAD C /* AC M[C] */ ADD D /* AC + M[D] */ MUL T /* AC * M[T] */ STORE X /* M[X] AC */ Zero-Address Instructions - Can be found in a stack-organized computer - Program to evaluate X = (A + B) * (C + D) (REVERSE POLISH NOTATION) A B + C D + *: PUSH ADD MUL POP Computer Organization A B C D X /* /* TOS A */ TOS B */ TOS (A + B) */ TOS C */ TOS D */ TOS (C + D) * (A + B) */ M[X] TOS */ Computer Architectures Lab

Central Processing Unit 12 Addressing Modes ADDRESSING MODES Addressing Modes * Specifies a rule for interpreting or modifying the address field of the instruction (before the operand is actually referenced) * Variety of addressing modes - to give programming flexibility to the user - to use the bits in the address field of the instruction efficiently Computer Organization Computer Architectures Lab

Central Processing Unit Addressing Modes 13 TYPES OF ADDRESSING MODES Implied Mode Address of the operands are specified implicitly in the definition of the instruction - No need to specify address in the instruction - EA = AC, or EA = Stack[SP] Immediate Mode Instead of specifying the address of the operand, operand itself is specified - No need to specify address in the instruction - However, operand itself needs to be specified - Sometimes, require more bits than the address - Fast to acquire an operand Register Mode Address specified in the instruction is the register address - Designated operand need to be in a register - Shorter address than the memory address - Saving address field in the instruction - Faster to acquire an operand than the memory addressing - EA = IR(R) (IR(R): Register field of IR) Computer Organization Computer Architectures Lab

Central Processing Unit Addressing Modes 14 TYPES OF ADDRESSING MODES Register Indirect Mode Instruction specifies a register which contains the memory address of the operand - Saving instruction bits since register address is shorter than the memory address - Slower to acquire an operand than both the register addressing or memory addressing - EA = [IR(R)] ([x]: Content of x) Register used in Register Indirect Mode may have Autoincrement or Autodecrement features - When the address in the register is used to access memory, the value in the register is incremented or decremented by 1 automatically Direct Address Mode Instruction specifies the memory address which can be used directly to the physical memory - Faster than the other memory addressing modes - Too many bits are needed to specify the address for a large physical memory space - EA = IR(addr) (IR(addr): address field of IR) Computer Organization Computer Architectures Lab

Central Processing Unit Addressing Modes 15 TYPES OF ADDRESSING MODES Indirect Addressing Mode The address field of an instruction specifies the address of a memory location that contains the address of the operand - When the abbreviated address is used large physical memory can be addressed with a relatively small number of bits - Slow to acquire an operand because of an additional memory access - EA = M[IR(address)] Relative Addressing Modes The Address fields of an instruction specifies the part of the address (abbreviated address) which can be used along with a designated register to calculate the address of the operand - Address field of the instruction is short - Large physical memory can be accessed with a small number of address bits - EA = f(IR(address), R is sometimes implied 3 different Relative Addressing Modes depending on R; * PC Relative Addressing Mode(R = PC) - EA = PC + IR(address) * Indexed Addressing Mode(R = IX, where IX: Index Register) - EA = IX + IR(address) * Base Register Addressing Mode(R = BAR, where BAR: Base Address Register) - EA = BAR + IR(address) Computer Organization Computer Architectures Lab

Central Processing Unit Addressing Modes 16 ADDRESSING MODES - EXAMPLES Address PC = 200 201 202 Memory Load to AC Mode Address = 500 Next instruction R 1 = 400 XR = 100 399 400 450 700 500 800 600 900 702 325 800 300 AC Addressing Effective Mode Address Direct address 500 Immediate operand Indirect address 800 Relative address 702 Indexed address 600 Register indirect 400 Autoincrement 400 Autodecrement 399 Computer Organization /* AC (500) /* AC 500 /* AC ((500)) /* AC (PC+500) /* AC (RX+500) /* AC R 1 /* AC (R 1)+ /* AC -(R) */ */ */ Content of AC 800 500 325 900 400 700 450 Computer Architectures Lab

Central Processing Unit Data Transfer and Manipulation 17 ADDRESSING MODES Data Transfer Instructions with Different Addressing Modes Assembly Convention Direct address LD ADR Indirect address LD @ADR Relative address LD $ADR Immediate operand LD #NBR Index addressing LD ADR(X) Register LD R 1 Register indirect LD (R 1) Autoincrement LD (R 1)+ Autodecrement LD -(R 1) Mode Computer Organization Register Transfer AC M[ADR] AC M[M[ADR]] AC M[PC + ADR] AC NBR AC M[ADR + XR] AC R 1 AC M[R 1], R 1 + 1 R 1 - 1, AC M[R 1] Computer Architectures Lab

Central Processing Unit 18 Program Control PROGRAM INTERRUPT Types of Interrupts External interrupts External Interrupts initiated from the outside of CPU and Memory - I/O Device -> Data transfer request or Data transfer complete - Timing Device -> Timeout - Power Failure - Operator Internal interrupts (traps) Internal Interrupts are caused by the currently running program - Register, Stack Overflow - Divide by zero - OP-code Violation - Protection Violation Software Interrupts Both External and Internal Interrupts are initiated by the computer HW. Software Interrupts are initiated by the executing an instruction. - Supervisor Call -> Switching from a user mode to the supervisor mode -> Allows to execute a certain class of operations which are not allowed in the user mode Computer Organization Computer Architectures Lab

Central Processing Unit 19 RISC: REDUCED INSTRUCTION SET COMPUTERS • An important aspect of computer architecture is the design of the instruction set for the processor. The instruction set chosen for a particular computer determines the way that machine language programs are constructed. • A computer with a large number of instructions is classified as a complex instruction set computer, abbreviated CISC. • 1980 s, a number of computer designers recommended that computers use fewer instructions with simple constructs so they can be executed much faster within the CPU without having to use memory as often. This type of computer is classified as a reduced instruction set RISC Computer Organization Computer Architectures Lab

Central Processing Unit 20 CISC Characteristics • One reason for the trend to provide a complex instruction set is the desire to simplify the compilation and improve the overall computer performance. • The task of a compiler is to generate a sequence of machine instructions for each high-level language statement. • The task is simplified if there are machine instructions that implement the statements directly. • The essential goal of a CISC architecture is to attempt to provide a single machine instruction for each statement that is written in a high-level language. – Examples of CISC architectures are the Digital Equipment Corporation VAX computer and the IBM 370 computer. Computer Organization Computer Architectures Lab

Central Processing Unit 21 • Another characteristic of CISC architecture is the incorporation of variable-length instruction formats. • Instructions that require register operands may be only two bytes in length, but instructions that need two memory addresses may need five bytes to include the entire instruction code. • The instructions in a typical CISC processor provide direct manipulation of operands residing in memory. • However, as more instructions and addressing modes are incorporated into a computer, the more hardware logic is needed to implement and support them, and this may cause the computations to slow down. Computer Organization Computer Architectures Lab

Central Processing Unit 22 • In summary, the major characteristics of CISC architecture are: 1. A large number of instructions-typically from 100 to 250 instructions 2. Some instructions that perform specialized tasks and are used infrequently 3. A large variety of addressing modes-typically from 5 to 20 different modes 4. Variable-length instruction formats 5. Instructions that manipulate operands in memory Computer Organization Computer Architectures Lab

Central Processing Unit 23 RISC Characteristics • The concept of RISC architecture involves an attempt to reduce execution time by simplifying the instruction set of the computer. The major characteristics of a RISC processor are: 1. Relatively few instructions 2. Relatively few addressing modes 3. Memory access limited to load and store instructions 4. All operations done within the registers of the CPU 5. Fixed-length, easily decoded instruction format 6. Single-cycle instruction execution 7. Hardwired rather than microprogrammed control 8. A relatively large number of registers in the processor unit 9. Efficient instruction pipeline Computer Organization Computer Architectures Lab

Central Processing Unit 24 • A characteristic of RISC processors is their ability to execute one instruction per clock cycle. This is done by overlapping the fetch, decode, and execute phases of two or three instructions by using a procedure referred to as pipelining. Computer Organization Computer Architectures Lab

Central Processing Unit RISC 25 CRITICISM ON COMPLEX INSTRUCTION SET COMPUTERS Complex Instruction Set Computers - CISC High Performance General Purpose Instructions - Complex Instruction -> Format, Length, Addressing Modes -> Complicated instruction cycle control due to the complex decoding HW and decoding process - Multiple memory cycle instructions -> Operations on memory data -> Multiple memory accesses/instruction - Microprogrammed control is necessity -> Microprogram control storage takes substantial portion of CPU chip area -> Semantic Gap is large between machine instruction and microinstruction - General purpose instruction set includes all the features required by individually different applications -> When any one application is running, all the features required by the other applications are extra burden to the application Computer Organization Computer Architectures Lab

Central Processing Unit 26 RISC PHYLOSOPHY OF RISC Reduce the semantic gap between machine instruction and microinstruction 1 -Cycle instruction Most of the instructions complete their execution in 1 CPU clock cycle - like a microoperation * Functions of the instruction (contrast to CISC) - Very simple functions - Very simple instruction format - Similar to microinstructions => No need for microprogrammed control * Register-Register Instructions - Avoid memory reference instructions except Load and Store instructions - Most of the operands can be found in the registers instead of main memory => Shorter instructions => Uniform instruction cycle => Requirement of large number of registers * Employ instruction pipeline Computer Organization Computer Architectures Lab

Central Processing Unit RISC 27 ADVANTAGES OF RISC Advantages of RISC - Computing Speed - Design Costs and Reliability - High Level Language Support • Computing Speed - Simpler, smaller control unit --> faster - Simpler instruction set; addressing modes; instruction format --> faster decoding - Register operation --> faster than memory operation - Identical instruction length, One cycle instruction execution --> suitable for pipelining --> faster Computer Organization Computer Architectures Lab

Central Processing Unit RISC 28 ADVANTAGES OF RISC • Design Costs and Reliability - Shorter time to design --> reduction in the overall design cost and reduces the problem that the end product will be obsolete by the time the design is completed - Simpler, smaller control unit --> higher reliability - Simple instruction format (of fixed length) --> ease of virtual memory management • High Level Language Support - A single choice of instruction --> shorter, simpler compiler - A large number of CPU registers --> more efficient code - Reduced burden on compiler writer Computer Organization Computer Architectures Lab