C 164 CI Block Diagram C 166 Core

C 164 CI Block Diagram C 166 -Core Data (C 164 CI-8 RM) or OTP CPU Instr. /Data 32 Data 16 Dual Port 64 K ROM 16 RAM 2 KByte (C 164 CI-8 EM) PLL-Oscillator prog. Multiplier: Watchdog 0. 5; 1; 1. 5; 2; 2. 5; 3; 4; 5 Interrupt Controller RTC 13 ext. IR 16 Interrupt Bus Peripheral Data 16 Port 4 BRG T 4 Port 3 Port 5 Timer 13 8/16 bit MUX only & XBUS Control 10 -Bit USART Sync. GPT 1 CAPCOM 2 CAPCOM 6 Unit for PWM Generation Channel ADC T 2 (SPI) 8 -Channels ASC SSC T 3 Timer 8 External Bus Timer 7 16 XBUS (16 -bit NON MUX Data / Addresses) P 4. 6/ CAN Tx. D Full-CAN Interface V 2. 0 B active Port 0 P 4. 5/ CAN Rx. D PEC External Instr. /Data 1 Comp. Channel Port 8 3/6 CAPCOM Channels Port 1 6 8 Embedded Systems 9 12. 08. 2013 4 16 Page 1

CPU – Block Diagram CPU STK UV Exec. Unit MDH SP Instr. Ptr. MDL STK OV Instr. Reg. 32 4 -Stage Pipeline On-Chip (EP)ROM PSW SYSCON Mul. /Div. -HW 16 STK UV Bit-Mask Gen. ALU 16 -bit Barrel-Shifter BUSCON 0 BUSCON 1 ADDRSEL 1 BUSCON 2 ADDRSEL 2 BUSCON 3 ADDRSEL 3 BUSCON 4 ADDRSEL 4 Data Page Pointer STK OV Context Ptr. On-Chip Static RAM R 15 General Purpose Registers 16 R 0 Code Seg. Ptr SFR Embedded Systems 12. 08. 2013 Page 2

Four stage instruction-pipeline Fetch Decode 1. Instr. 2. Instr. 3. Instr. 4. Instr. Execute Time Write Back 1 Machine Cycle = 100 ns at 20 MHz CPU clock ¨ ¨ 100 ns effective execution time (20 MHz f. CPU), TCLK = 50 ns (1 machine cycle requires 2 CPU Clocks, i. e. 100 ns ) Three Pre-Fetch-Steps in word size (Bus Controller) for supporting of the Pipeline Optimized execution of jumps – For jump instructions (Jump, Cond. Jump, Call, Return, . . . ) usually one additional machine cycle is necessary, to fetch the instruction at the destination address Jump Cache – For the execution of loops no additional machine cycle is necessary Embedded Systems 12. 08. 2013 Page 3

Arithmetic Logic Unit A B Logic Operations: Cout Cin ALU flags op Shift / Rotate: Z Arithmetic Operations: add sub inc dec neg Embedded Systems and nand or nor exnor not sll sla rol sra ror s/ro : shift/rotate l/r : left/right l/a : logic (unsigned)/arithmetic (signed) 12. 08. 2013 Page 4

General Purpose Register (GPR) ¨ 16 GPRs form a register bank which consits of maximize – 8 Word-Registers and – 8 Word-Registers with byte access to the least significant and most significant byte ¨ ¨ The GPRs are bit-addressable the register banks can be arranged in the internal RAM in any order The mapping of the active register bank is determined by the Context Pointer (CP) CP can easily changed to choose an other register bank “Switch Context”-instruction. Embedded Systems 12. 089. 2013 Page 6

2 k. Byte internal RAM – mapping of the register banks and the stack RH 7 RH 6 RH 5 RH 4 RH 3 RH 2 RH 1 RH 0 Stackpointer Underflow Stackpointer Overflow RL 7 RL 6 RL 5 RL 4 RL 3 RL 2 RL 1 RL 0 R 15 R 14 R 13 R 12 R 11 R 10 R 9 R 8 R 7 R 6 R 5 R 4 R 3 R 2 R 1 R 0 2 KBytes internal RAM 0 FDFE R 15 R 0 Context pointer 0 FC 00 STKUV SP STKOV 0 F 600 STKOV Embedded Systems 12. 08. 2013 Page 7

Address Space ¨ Complete address space: – 64 k. Byte non-segmented address space – Up to 4 MBytes segmented address spaces: 64 k. Byte Code-Segments and 16 k. Bytes Data-Pages – “von Neumann”-Architecture, which is internally equipped with Multi. BUS-Structures to avoid BUS-Bottlenecks ¨ Internal Address Space – 2 KByte RAM – 64 KBytes Flash/OTP ROM (One Time Programmable ROM) (C 164 CI-8 FM) ¨ Flexible external BUS-Configurations – Up to 22 -Bit Address-BUS / 8 -Bit Data-BUS (multiplexed) – Up to 22 -Bit Address -BUS / 16 - Bit Data-BUS (multiplexed) – 5 completely independent configuration-registers – 4 programmable “Chip Selects” and programmable BUS-control signals help to avoid external logic. Embedded Systems 12. 08. 2013 Page 8

Internal and external address mapping of the C 164 CI Segment 0 contains the internal memory 7 0. 5 k 0 512 Bytes SFR’s Internal RAM 2 k Internal RAM Reserved 0. 5 k 512 Bytes ESFR’s Full -CAN Reserved 0 x 010000 Code Segments Daten Pages 0 x 040000 0 x 00 FE 00 15 14 0 x 00 FA 00 3 0 x 030000 0 x 00 F 600 0 x 00 F 200 13 12 11 2 10 9 0 x 00 F 000 0 x 020000 8 7 0 x 00 E 800 1 Bit-adressierbarer Bereich X-Bus Peripheral Up to 4 MBytes 6 5 External Memory 0 x 010000 4 Internal ROM/ FLASH 2*32 k 3 32 k Internal ROM / Flash E²PROM (can be mapped to Segm. 1 ) Embedded Systems 0 x 008000 0 2 1 0 x 000000 25. 9. 2013 0 x 000000 0 Page 9

The programming language C for the C 164 C 166 is the realisation of ANSI-C for the microcontroller-family C 166. The C 166 -Compiler provides a number of extensions of the ANSI-C Standard. Ispecially such, that directly support the C 166 -architecture: C 166 -denotation commentary memory types As completition to the „storage class" to every definition of a variable a „memory type " can be specified. This allows a from the current „memory model" independent addressing of variables in different address spaces of the 166 -systems. Following typs are defined: sfr near, idata, bdata, sdata, far, huge, xhuge. Is used as declaration of "Special-Function-Register" (SFR) of the 166 -family sbit Declaration of Bits within SFR's. bit Data type bit. Return values and passing parameters of functions can be of type bit-addressable Variables in bit addressable space can be defined as memory type by means of bdata. Embedded Systems 12. 8. 2013 Page 10

The programming language C for the microcontroller C 164 C 166 -denotation commentary register bank (using) Each function can contain a declaration, in which the register bank to be used can be set. interrupt Functions can declared als Interrupt-Service-Routines by indication of the interrupt names respectively – vectors. register mask The C 166 -Compiler generates for each C-function a registermask, in which the registers used by the function are listed. Those can be used as funktion prototype, due to optimize the usage of the registers. RTX 166 tasks By the keyword _task_ the functions is specified as a task of the operating system RTX 166. New Keywords (summary): Memory types: near, idata, bdata, sdata, far, huge, xhuge Data types: bit, sfr, sbit Functions: interrupt, _task_, using Embedded Systems 12. 08. 2013 Page 11

The programming language C for the microcontroller C 164 Memory Types Type Address space near 16 -Bit addresses up to 64 k. Bytes idata On-chip RAM (fastest access) bdata Bit-addressable On-chip-RAM sdata System Page (0 x. C 000 -0 x. FFFF) inclusive SFR‘s far 32 -Bit Pointer with 16 -Bit address calculation, the size of the object is 16 k. Byte. huge 32 -Bit Pointer with 16 -Bit, address calculation, the size of the object is 32 k. Byte. xhuge 32 -Bit Pointer with 32 -Bit address calculation, the size of the object is 16 MByte. Embedded Systems 12. 08. 2013 Page 12

The programming language C for the microcontroller C 164 ¨ ¨ According to the memory types memory models can be predeterminded as presettings, which always will be used, when no memory type is explicitly specified by the variable – or function This is done by the preprocessor directive: # pragma storage model Storage model Variable functions Segmentation Code size TINY SMALL COMPACT HCOMPACT MEDIUM LARGE HLARGE near far huge near near far far no yes yes yes 64 k 64 k unlimited Embedded Systems 12. 08. 2013 Page 13

The programming language C for the microcontroller C 164 Data types: : size of memory and range of values Datentyp size of memory range of values bit # signed char unsigned char signed int unsigned int signed long unsigned long float double pointer 1 Bit 1 Byte 2 Bytes 4 Bytes 8 Bytes 2/4 Bytes 0 or 1 -128 to +127 0 to 255 -32768 to + 32767 0 to 65535 -2147483648 to +2147483642 0 to 4294967295 1. 176 E-38 to 3. 40 E+38 1. 7 E-308 to 1. 7 E+308 Address of the object Datatypes for the access to Special Function Registers (SFR) sbit # sfr # 1 Bit 2 Bytes 0 or 1 0 to 65535 # special data types in C 166, which are not defined in ANSI-C. Embedded Systems 12. 08. 2013 Page 14

Integrated Development Environment – µVision 2 Editor / Project Management Macro. Assembler ANSI C Compiler CLibrary RTX Tiny Library Real Time Operating System Manager Linker / Locater – Debugger – Simulator Emulator & PROM Programmer CPU & Peripheral Simulator Embedded Systems Monitor Target Debugging 12. 08. 2013 Start of lab practical Page 15

Code-addressing using segmentation in the 4 MByte address space Code Segment Pointer (CSP) for Code-Addressing 15 14 13 0 8 7 6 5 Code Seg. Pointer 15 14 13 8 7 16 -Bit Instr. Pointer 0 6 -Bit Segmentnumber 16 -Bit 22 -Bit physical Code-Addresse (C 164) The Instruction Pointer (IP) is incremented after each instruction fetch phase The Code Segment Pointer (CSP) is only changed by absolute jumps, respectively indirect y in case of the return from a subroutine by the stack Embedded Systems 12. 08. 2013 Page 16

Addressing of data by paging within the 4 MByte Address space Data addressing via the Data Page Pointer (DPP) 15 14 13 16 -bit Adresse 0 Selection of a Data Page Pointer DPP 3 DPP 2 DPP 1 DPP 0 10 -bit 14 -bit Pagenumber Physical 24 -Bit Data-Address (up to 22 external available for C 164) SFR Embedded Systems 25. 9. 2009 Page 17

External Bus Controller ¨ ¨ ¨ Allows variable timing of CPU-controlling signals by software Realizes up to 4 Chip-Select-Signals Selection of 4 address ranges possible Special Function Register BUSCON 0. . 4 Programmable timings Determinition of CS# - signals Selection of the bandwith of the Data-BUS 8 / 16 Bit Special Function Register ADDRSEL 1. . 4 Programmable ranges of the address space for the access to external components with the properties of the assigned BUSCONx- registers. Embedded Systems 12. 08. 2013 Page 18

Interrupts ¨ ¨ The architecture of the C 164 supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal (e. g. Timer overrun) or external to the microcontroller ( e. g. level change at an input port pin). These mechanisms include: Normal Interrupt Processing The CPU temporarily suspends the current program execution and branches to an interrupt service routine in order to service an interrupt requesting device. The current program status (IP, PSW, in segmentation mode also CSP) is saved on the internal system stack. -Powerful prioritisation in 15 priority levels, each in 4 groups - Short interrupt-reaction times: Min. 250 ns, typical 400 ns (@20 MHz) Embedded Systems 25. 9. 2009 Seite 19

Normal Interrupt Processing ¨ ¨ - for each activated interrupt source an function, the Interrupt Service Routine (ISR) has to be programmed - The necessary Interrupts must be activated. This is done via a dedicated Interrupt Enable Flag in the Interrupt Control Register of the source - Additionally there is an global Interrupt Flag (IEN) for general Enabling and Disabling in the PSW (Prozessor status word) Threfore an ISR is executed, if - The global interrupt enable bit (EIN) is set - the individul interrupt enable bit (xx. IE) is set - the interrupt event occurs Embedded Systems 25. 9. 2009 SFR Seite 20

Special Function Registers of the Interrupt System ¨ Interrupt Control Register - The Interrupt Control Register of all interrupt sources are organized identically, xx is the code of the associated interrupt source. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - xx. IR xx. IE ILVL GLVL - - - - r/w r/w –GLVL: – –ILVL: Group Level ; Defines the internal order for requests of the same priority 11: highest group priority 00: lowest group priority Interrupt priority level FH: highest priority level 0 H: lowest priority level –xx. IE: Interrupt Enable Control Bit 0: Interrupt is disabled 1: Interrupt is enabled –xx. IR: Interrupt Request Flag. 0: No request pending 1: This source has raised an interrupt request The Interrupt Request Flag is set by hardware whenever a service request from the respective source occurs. It is cleared automatically upon entry in the interrupt service routine or upon a PEC service. Embedded Systems 25. 9. 2009 Seite 21

Interrupt Vector Table The C 164 provides a vectored interrupt system. In this system specific vector locations in the memory space are reserved for the interrupt service functions. Whenever a request occurs, the CPU branches to the location that is associated with the respective interrupt source. Embedded Systems 25. 9. 2009 Seite 22

Interrupts und PEC - Priorisation PEC 7 group 3 Level 15 PEC 3 group 2 Level 14 group 3 group 2 Level 1 -13 group 3 (Level 0) Embedded Systems group 2 group 1 PEC 5 PEC 1 group 1 PEC 4 Group group 0 3 2 1 0 PEC 0 group 0 Level group 3 PEC 6 group 0 12. 08. 2013 15 64 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 Page 23

Interrupt Processing INTR Service: Interrupt Control Register of the triggering peripheral-elements Rescuing: PSW, CSP, IP INTR Flag is set Periph. Interrupt Priority-Check Periph. Interrupt Comparision of the interrupt priority with the run-time-priority of the CPU If more Interrupts on the same level Group Check New CPU-Prio. in PSW. Clear INTR Flag Periph. Interrupt External Interrupt* CSP and IP from peripherie-vector or trap-number PEC Service 16 Priority-Levels 4 Groups * External Interrupts are possible e. g. instead of the “Capture” Inputs 32 Peripheral Interrupts 13 ext. Interrupts (+ NMI) including 4 “fast” interrupts I-Vektor-Tabelle Embedded Systems SFR 07. 02. 2015 Dave v 1_isr Dave µV-v 1_isr Page 24

Interrupt Priority Level and Group Level The four bits of bit field ILVL specify the priority level of a service request for the arbitration of simultaneous requests. The priority increases with the numerical value of ILVL, so 0000 B is the lowest and 1111 B is the highest priority level. ¨ When more than one interrupt request on a specific level gets active at the same time, the values in the respective bit fields GLVL are used for second level arbitration to select one request for being serviced. Again the group priority increases with the numerical value of GLVL, so 00 B is the lowest and 11 B is the highest group priority. ¨ Upon entry into the interrupt service routine, the priority level of the source that won the arbitration and who’s priority level is higher than the current CPU level, is copied into bit field ILVL of register PSW after pushing the old PSW contents on the stack. ¨ The interrupt system of the C 164 allows nesting of up to 15 interrupt service routines of different priority levels (level 0 cannot be arbitrated). Embedded Systems 25. 9. 2009 Seite 25

Saving the Status during Interrupt Service ¨ ¨ ¨ Before an interrupt request that has been arbitrated is actually serviced, the status of the current task is automatically saved on the system stack. The CPU status (PSW) is saved along with the location, where the execution of the interrupted task is to be resumed after returning from the service routine. This return location is specified through the Instruction Pointer (IP) and, in case of a segmented memory model, the Code Segment Pointer (CSP). Bit SGTDIS in register SYSCON controls, how the return location is stored. The system stack receives the PSW first, followed by the IP (unsegmented) or followed by CSP and then IP (segmented mode). This optimizes the usage of the system stack, if segmentation is disabled. The CPU priority field (ILVL in PSW) is updated with the priority of the interrupt request that is to be serviced, so the CPU now executes on the new level Embedded Systems 25. 9. 2009 Seite 26

Task Status saved on the System Stack Embedded Systems 25. 9. 2009 Seite 27

Saving the Status during Interrupt Service ¨ The interrupt request flag of the source that is being serviced is cleared. The IP is loaded with the vector associated with the requesting source (the CSP is cleared in case of segmentation) and the first instruction of the service routine is fetched from the respective vector location, which is expected to branch to the service routine itself Embedded Systems 25. 9. 2009 Seite 28

Interrupt Processing with Peripheral Events Controller (PEC) ¨ Interrupt Processing with Peripheral Events Controller (PEC) – Releases the CPU from simple and frequently arising ISR’s – Interrupt controlled “DMA-simular” data transfer with CPUparticipation – Reaction times: Min. 150 ns, typical 300 ns @20 MHz A faster alternative to normal software controlled interrupt processing is servicing an interrupt requesting device with the C 164’s integrated Peripheral Event Controller (PEC). Triggered by an interrupt request, the PEC performs a single word or byte data transfer between any two locations in segment 0 (data pages 0 through 3) through one of eight programmable PEC Service Channels. During a PEC transfer the normal program execution of the CPU is halted for just 1 instruction cycle. No internal program status information needs to be saved. The same prioritization scheme is used for PEC service as for normal interrupt processing. PEC transfers share the 2 highest priority levels. Embedded Systems 12. 08. 2013 Page 29

Peripheral Events Controller (PEC) Interrupt has passed priority- and group-check Interrupt Priority 14 or 15 and Data Counter > 0 Interrupt Priority < 14 Interrupt Service PEC Service Memory Segment 0 0 x. FFFF Peripheral Events Contoller INTR Service: 8 PEC Channels Rescuing: PSW, CSP, IP New CPU-Prio. in PSW. CSP and IP from peripheral-vector or Trap-Number Prioritäts- & Group Check Data Counter SRC Pointer DEST Pointer Interrupt if Data Counter = 0 Dave v 1_isr_pec SFR Embedded Systems Contr. Reg. 12. 08. 2013 Byte bzw. Word Transfer 0 x 0000 Demo v 1 a_isr_pec Page 30

Characteristics of interrupt pogramming ¨ ¨ ¨ ISR as short as possible Data exchange between ISR and main only via static modul global variables and global functions Note: ISR‘s don‘t have a return value Embedded Systems 25. 9. 2009 Seite 31