BuiltIn SelfTest for Multipliers Mary Pulukuri Dept of

Built-In Self-Test for Multipliers Mary Pulukuri Dept. of Electrical & Computer Engineering Auburn University M. Pulukuri 9/09 VLSI D&T Seminar

Outline of Presentation q. Overivew of multiplier architectures q. History of Digital Signal Processor (DSP) Architectures in FPGAs v. Overview of Virtex-4 DSP q. Prior Testing R&D for Multipliers q. Our Approach q. Analysis Methodology q. Simulation Results q. Application to Virtex-4 & 5 DSPs q. Summary and Conclusions M. Pulukuri 9/09 VLSI D&T Seminar 2

Overview of Multipliers q. Array Multiplier v. Final product calculated by using an array of full adders & and gates M. Pulukuri 9/09 VLSI D&T Seminar 3

Overview of Multipliers q. Signed array or Baugh Wooley multiplier v. Final product calculated using an array of full adders, and gates & nand gates M. Pulukuri 9/09 VLSI D&T Seminar 4

Overview of Multipliers q Modified Booth multipliers v Partial products calculated using the modified booth algorithm ü Modified booth algorithm uses a binary encoder to calculate partial products using a series of shift operations v Summation of partial products done using CLA adders A. R. Cooper, “Parallel architecture modified Booth multiplier” IEEE Proc. Electronic Circuits and Systems, vol. 135, no. 3, pp. 125 -128, 1998 M. Pulukuri 9/09 VLSI D&T Seminar 5

Overview of Multipliers q Modified Booth/Wallace Tree multipliers v. Summation of partial products done using a Wallace Tree ü Each column of partial products are summed using a multistage setup of half and full adders ü Each multi-stage adder circuit generates a sum and carry which form the two final partial products v. Two final stage partial products from the wallace tree are added using a CLA adder M. Pulukuri 9/09 VLSI D&T Seminar 6

Xilinx FPGA Architectures q 4000/Spartan v. Nx. N array of unit cells üUnit cell = CLB + routing ü Fast carry logic in CLBs for adders q. Virtex/Spartan-2 v. Mx. N array of unit cells ü Carry logic + AND gate for array multipliers v 4 K block RAMs at edges PC PC q. Virtex-2/Spartan-3 v 18 K block RAMs in array v 18 x 18 -bit multipliers with each RAM ü “based on modified Booth architecture” PC q. Virtex-4/Virtex-5 v. Added 48 -bit DSP cores w/multipliers M. Pulukuri 9/09 VLSI D&T Seminar PC 7

Virtex-4 DSP Architecture Outputs w/ dedicated routing q 2 DSP slices per tile v 16 -256 tiles in 1 -8 columns X A(18) B(18) Y q Each DSP includes: C(48) v 18 x 18 -bit 2's-comp multiplier (w/o adder) v 3 -input, 48 -bit adder/subtractor P (48) X A(18) B(18) Y v Configuration bits control other MUXs M. Pulukuri 9/09 Inputs for cascading Outputs w/ dedicated routing ü For X, Y, & Z MUXs ü Pipelining registers ü Accumulator register ü Easily tested P (48) Z ü P = Z (X+Y+Cin) ü Optional accum reg v User controlled operational modes Z Inputs for cascading VLSI D&T Seminar 8

BIST Approach for Virtex-5 DSP Larger multiplier M. Pulukuri 9/09 VLSI D&T Seminar 9

Multiplier Architectures q Test algorithm depends on architecture v. But architecture is not specified in data sheets ü Eliminate sequential logic architectures ü “Based on modified Booth” q Multiplier choices include: v. Array v. Booth v. Modified Booth/Wallace tree ü Our assumption based on area/performance analysis q Our goal: find/develop architecture independent test algorithm(s) M. Pulukuri 9/09 VLSI D&T Seminar 10

Modified Booth Test Algorithms q. Test algorithm uses 8 -bit counter (256 vectors) v“ “Effective Built-In Self-Test for Booth Multipliers” üGizopoulos, Paschalis & Zorian Ø IEEE Design & Test of Computers pp. 105 -111, 1998 Ø Claim fault coverage ~ 99. 8% ü 4 x 4 connections to multiplier inputs Ø Order of the bits does not matter Ø Algorithm used in Srinivas Garimella’s MS thesis for Virtex-2 multipliers M. Pulukuri 9/09 VLSI D&T Seminar 4× 4 algorithm 8 -bit counter MSB 4 n Booth encoding LSB 4 n × 2 n n×n multiplier 11

Modified Booth Test Algorithms q Test algorithm uses 8 -bit counter (256 vectors) v“An Effective BIST Architecture for Fast Multiplier Cores” ü Paschalis, Kranitis, Psarakis Gizopoulus & Zorian Ø Proc. Design, Automation and Test in Europe Conf. pp. 117 -121, 1999 Ø Claim fault coverage ~99. 8% ü 5 x 3 connections with 5 inputs to Booth encoding Ø But this was not explicit in paper § Only shown in figure Ø Order of the bits does not matter 5× 3 algorithm 8 -bit counter MSB 5 n Booth encoding LSB 3 n × 2 n n×n multiplier v. Note that this paper is from 1999 M. Pulukuri 9/09 VLSI D&T Seminar 12

Modified Booth Test Algorithms q Test algorithm uses 8 -bit counter (256 vectors) v“Low Power BIST for Wallace Tree-based Fast Multipliers” ü Bakalis, Kalligeros, Nikolos, Vergos & Alexiou Ø Proc. Int. Symp. on Quality of Electronic Design, pp. 433 -438, 2000 Ø Claim fault coverage > 99% ü 5 x 3 connections with 5 inputs to Booth encoding Ø Specifically stated in paper § But no data to back up claim that 5 x 3 better than 3 x 5 Ø Did they just observe it in Zorian paper? 5× 3 algorithm 8 -bit counter MSB 5 n Booth encoding LSB 3 n × 2 n n×n multiplier § Note that this paper was published a year later than Zorian M. Pulukuri 9/09 VLSI D&T Seminar 13

Modified Booth Test Algorithms q. Test algorithm uses 8 -bit counter (256 vectors) v. But which side is Booth encoding? üXilinx does not specify v. Our original approach üRun 5 x 3 algorithm Ø 256 vectors üand run 3 x 5 algorithm Ø 512 vectors üInclude 4 x 4 if fault coverage improves Ø 768 vectors 5× 3 3× 5 algorithm 8 -bit counter MSB 53 n Booth encoding LSB 35 n × 2 n n×n multiplier üAdditional algorithms only require multiplexers to change inputs Ø Use same 8 -bit counter M. Pulukuri 9/09 VLSI D&T Seminar 14

Methodology for Analysis q Multipliers evaluated v. Unsigned array v. Signed array – Baugh Wooley v. Modified Booth ü Carry look-ahead adders sum partial products in every stage v. Modified Booth Wallace Tree ü Carry look-ahead adder sums final stage partial products ü Carry select adder sums final stage partial products ü Ripple carry adder sums final stage partial products M. Pulukuri 9/09 VLSI D&T Seminar 15

Methodology for Analysis q. Designed 8 -bit models of the multipliers q. Fault model: Collapsed single stuck-at gate level faults q. Exhaustive testing üTo determine undetectable faults q. Test algorithms evaluated ü 4× 4 ü 5× 3 ü 3× 5 ü 5× 3 & 3× 5 ü 4× 4, 5× 3 & 3× 5 M. Pulukuri 9/09 VLSI D&T Seminar 16

Multiplier Total Faults Unsigned array 1648 Signed array 1648 Mod-Booth 2499 Mod-Booth 2184 Wall-Tree CLA Mod-Booth 2422 Wall-Tree CSA Mod-Booth 2021 Wall-Tree RCA M. Pulukuri 9/09 Test Algorithm # faults detected (effective fault coverage) Exhaust 4× 4 5× 3 3× 5 1644 (100) 2196 (100) 2090 (100) 2243 (100) 1962 (100) 1644 (100) 2180 (99. 27) 2061 (98. 61) 2215 (98. 75) 1937 (98. 73) 1644 (100) 2168 (98. 72) 2068 (98. 95) 2217 (98. 84) 1944 (99. 08) 1621 (98. 60) 1644 (100) 2179 (99. 23) 2070 (99. 04) 2218 (98. 89) 1944 (99. 08) VLSI D&T Seminar 5× 3 & 3× 5 1644 (100) 2182 (99. 36) 2071 (99. 09) 2222 (99. 06) 1944 (99. 08) 5× 3, 3× 5 & 4× 4 1644 (100) 2193 (99. 86) 2074 (99. 23) 2228 (99. 33) 1947 (99. 24) 17

Application to Virtex-4 & 5 DSPs q In Virtex-4 & 5 DSPs v. Final stage carry look-ahead adder (CLA) separated from the multiplier v 5× 3 & 3× 5 give the same fault coverage for the multiplier alone v. Separate test algorithm for the CLA ü Run both 5× 3 and 3× 5 to test for bridging faults on the cascade routing between adjacent slices Mode (Test) First 256 ccs Second 256 ccs Third 256 ccs Fourth 256 ccs 00 (multiply) P = A×B+C P = A: B+C M. Pulukuri 9/09 VLSI D&T Seminar 18

Summary and Conclusion q If the architecture of the multiplier is not known: v 3× 5 algorithm gives best overall fault coverage for most multipliers ü Contradicting the claim of the authors who proposed 5× 3 v. Running 3× 5 & 5× 3 gives better fault coverage for all multipliers v. Running all three algorithms: 3× 5, 5× 3 and 4× 4 test algorithms provides the best fault coverage for all multipliers ü Architecture independent testing q Virtex-4 & Vritex-5 multipliers v. Original approach was 3× 5 and 5× 3 v. Better approach would be 3× 5 and 4× 4 M. Pulukuri 9/09 VLSI D&T Seminar 19

Summary and Conclusion q For multipliers in Virtex-2 FPGAs v. Adder not separated from the multiplier ü Run both 3× 5 and 5× 3 algorithms Ø These give highest fault coverage for multiplier & CLA q The 3× 5 and 4× 4 BIST algorithm should be applied to multipliers in v. Spartan-3 A ü Similar to multipliers in Virtex-4 v. Spartan-6 ü Similar to multipliers in Virtex-4 v. Virtex-6 ü Similar to multipliers in Virtex-5 v. If only 2 algorithms can be applied ü Best results if all 3 can be applied M. Pulukuri 9/09 VLSI D&T Seminar 20

Summary and Conclusion q Area overhead for different approaches v. In addition to 8 -bit counter v. Maximum area overhead for N-bit multiplier: ü One test algorithm: 2 N 2: 1 multiplexers ü Two test algorithms: 2 N 3: 1 multiplexers Ø 1 additional counter bit for control ü All three test algorithms: 2 N 4: 1 multiplexers Ø 2 additional counter bits for control v. This is worst case since synthesis tools may reduce multiplexers ü Particularly in case of two and three test algorithms Ø Due to counter duplicate bits to same multiplexers v. Regardless, this is an area efficient BIST approach ü Paper almost finished for JETTA Letter or Trans. IE Corr. q Brad is using 3× 5, 5× 3 & 4× 4 algorithms in test bench for multipliers in Output Response Analyzer (ORA) for mixed signal BIST M. Pulukuri 9/09 VLSI D&T Seminar 21

M. Pulukuri 9/09 VLSI D&T Seminar 22