Built In Self Test Sungho Kang Yonsei University

Outline l l l Introduction Pattern Generation Response Analysis BIST Architectures Conclusion Computer Systems Lab. YONSEI UNIVERSITY 2

Built In Self Test l Introduction Capability of a product to carry out an explicit test of itself § Test patterns are generated on-chip § Responses to the test patterns are also evaluated on chip § External operations are required only to initialized the built-in tests and to check the test results (go/no-go) Computer Systems Lab. YONSEI UNIVERSITY 3

Built In Self Test l Introduction Advantage § No need for expensive tester § At-speed testing § Thorough test l Disadvantages § § § Initial Design Investment Area overhead Pin overhead Not effective for random testing resistive circuits Aliasing problem Computer Systems Lab. YONSEI UNIVERSITY 4

Test Pattern Generation l l l Pattern Generation Stored Pattern Exhaustive Pattern Pseudo Random Pattern Weighted Random Pattern Computer Systems Lab. YONSEI UNIVERSITY 5

Stored Pattern l l l Pattern Generation Store deterministic test patterns in a ROM Can achieve high fault coverage Requires large memory space Requires external ATPG and fault simulation Not practical or cost effective for large circuits Computer Systems Lab. YONSEI UNIVERSITY 6

Exhaustive Pattern l l Pattern Generation For n input combinational circuit, 2 n exhaustive patterns are required For large n, it is not practical Detects all irredundant, combinational faults Uses binary counters or LFSRs Computer Systems Lab. YONSEI UNIVERSITY 7

Exhaustive and Pseudo Exhaustive l Pattern Generation Possible required § Fault free simulation § Way to make segmentation l Not required § Fault simulation § Circuit modification l l Very high fault coverage Pattern generation § Use counters or LFSRs Computer Systems Lab. YONSEI UNIVERSITY 8

Pseudo Exhaustive Pattern l l l Pattern Generation Used when exhaustive test is too long Divide circuits into subcircuits Individual output verification (Cone verification) § Exhaustive test of each output § No output depends on all inputs l Segment verification § Network partitioned § Exhaustive test of each segment Computer Systems Lab. YONSEI UNIVERSITY 9

Combinational Circuit Classification l Partial Dependence Circuit (PDC) § § l Pattern Generation No output depends on all inputs Exhaustive test if possible Else output verification test Else segment verification Full Dependence Circuit (FDC) § Some output depends on all inputs § Exhaustive test if possible § Else segment verification Computer Systems Lab. YONSEI UNIVERSITY 10

Cone Verification l l Pattern Generation The p output circuit is logically divided into p cones Each cone is tested exhaustively All cones are tested concurrently (n, w) CUT § n inputs and output Yi = fi(Xi), w = maxi { |Xi| } l Example : (4, 2) CUT § If w=n, pseudo exhaustive testing is exhaustive testing Computer Systems Lab. YONSEI UNIVERSITY 11

Cone Verification l Pattern Generation LS 630 (16 bit error detection and correction) § § 24 inputs, 6 outputs Each output depends on 10 inputs 210 patterns for each output 6 X 210 patterns for all Computer Systems Lab. YONSEI UNIVERSITY 12

PDC Classification l Pattern Generation MTC § Maximal Test Concurrency Circuit § The number of test signals required ÄThe maximum number of inputs connected to any output § MTC Example Ä4 test vectors required ÄA = C ÄMinimal number of required test signals is equal to the maximum number of inputs upon which any output depends Computer Systems Lab. YONSEI UNIVERSITY 13

PDC Classification l Pattern Generation NMTC § Non-Maximal Test Concurrency Circuit § The number of test signals required ÄMore than the maximum number of inputs connected to any output § NMTC Example ÄEvery output is a function of only 2 inputs ÄEach output can still be tested exhaustively by 4 patterns Computer Systems Lab. YONSEI UNIVERSITY 14

PDC Classification l Pattern Generation NMTC Example § Every output is a function of only 2 inputs § Each output can be tested exhaustively by 5 patterns Computer Systems Lab. YONSEI UNIVERSITY 15

NMTC l Pattern Generation Identification of minimal set of test signals § Partition the circuit into disjoint subcircuits § For each disjoint subcircuit ÄGenerate a dependency matrix ÄPartition the matrix into groups of inputs so that 2 or more inputs in a group do not affect the same output ÄCollapse each group to form an equivalent input, called a test signal input § Characterize the collapsed matrix in terms of p and w where p is the number of partitions (width) and w is the maximum number of 1 s in any row (weight) § Construct the test pattern for the circuit Äp=w : MTC and test set consists of all 2 p patterns Äp=w+1 : test set consists of all possible patterns of p with either odd or even parity Äp>w+1 : test set consists of 2 or more pattern subsets, each of which contains all possible patterns of p bits having a specific constant weight Computer Systems Lab. YONSEI UNIVERSITY 16

NMTC Example l Example circuit l Dependency matrix § Dij = 1 if output I depends on input j ; otherwise Dij=0 Computer Systems Lab. YONSEI UNIVERSITY 17

NMTC Example l Reordering and grouping the inputs produce the following modified matrix Computer Systems Lab. YONSEI UNIVERSITY 18

NMTC Example l l In each group there must be less than two 1 s in each row and the number of groups should be minimal This insures that no output is driven by more than one input from each group § Finding such a partition is NP-complete l ORing each row within a group to form a single column Computer Systems Lab. YONSEI UNIVERSITY 19

NMTC Example l p=4 and w=3 § odd parity § § § § § ABCD 0 0 0 1 0 0 1 1 1 1 0 § Pseudo exhaustive test set consists of 8 patterns instead of 128 § Among 4 groups, 8 patterns using any 3 inputs are necessary Computer Systems Lab. YONSEI UNIVERSITY 20

NMTC l l Total number of test patterns is a function of p and w Constant weights do not exist for all pairs of p and w § For such cases, w can be increased so as to achieve a constantweight pseudo exhaustive test, but it may not be minimal in length l It is always easy to construct a circuit to generate a pseudo exhaustive test set for p>w+1 and hardware overhead of some of these circuits is quite high Computer Systems Lab. YONSEI UNIVERSITY 21

Segment Verification Pattern Generation l Segmentation testing via path sensitization l Sensitized path is established from C to F § Use 2 n 1+2 n 2 patterns instead of 2 n 1+n 2 patterns Computer Systems Lab. YONSEI UNIVERSITY 22

FDC l Pattern Generation LS 181 (ALU) § 14 inputs, 8 outputs § Some outputs depends on all inputs § 214 patterns l Use segmentation § Only 356 patterns are required Computer Systems Lab. YONSEI UNIVERSITY 23

Segment l Pattern Generation Example § Exhaustive test vectors : 64 § Output cone test vectors : 32 Computer Systems Lab. YONSEI UNIVERSITY 24

Segment Example l Pattern Generation Example Computer Systems Lab. YONSEI UNIVERSITY 25

Segment Example l Pattern Generation Exhaustive test of G sensitized to F 2 by Z = 1 § U V W X Y Z G H F 1 F 2 § 0 0 0 1 1 1 § 0 0 1 1 § 0 1 1 1 0 0 § 1 0 0 1 1 1 § 1 0 1 1 § 1 1 0 1 1 1 § 1 1 1 Computer Systems Lab. YONSEI UNIVERSITY 26

Segment Example l Pattern Generation Added to exhaustive test of G § U V W X Y Z G H F 1 F 2 § 0 0 0 1 1 1 § 0 0 1 1 § 0 1 1 1 0 0 § 1 0 0 1 1 1 § 1 0 1 1 § 1 1 0 1 1 1 § 1 1 1 0 1 0 § 0 0 1 0 Computer Systems Lab. YONSEI UNIVERSITY 27

Segment Example l Pattern Generation Added to exhaustive test of H § § § U V W 0 0 0 1 0 1 1 1 1 1 0 X 0 0 1 1 1 0 Computer Systems Lab. Y 0 1 0 1 1 1 Z 1 1 1 1 0 0 G 1 1 1 0 1 1 1 H F 1 F 2 1 1 1 0 0 0 1 1 1 1 1 0 0 YONSEI UNIVERSITY 28

Segment Example l Pattern Generation Added to exhaustive test of F 1 § § § U V W 0 0 0 0 1 0 1 1 1 1 1 0 X 0 0 1 1 1 0 Computer Systems Lab. Y 0 1 0 1 1 1 Z 1 1 1 1 0 0 G 1 1 1 0 1 1 1 H F 1 F 2 1 1 1 0 0 0 1 1 1 1 1 0 1 0 0 YONSEI UNIVERSITY 29

Segment Example l l l Pattern Generation Segmentation by multiplexors Path sensitization : 10 Multiplexors : 13 Computer Systems Lab. YONSEI UNIVERSITY 30

Segment l Pattern Generation 74181 ALU § 214 exhaustive patterns § Output cone test : 214 patterns Computer Systems Lab. YONSEI UNIVERSITY 31

Segment l Pattern Generation 74181 ALU § Li function : 16 patterns Computer Systems Lab. YONSEI UNIVERSITY 32

Segment l Pattern Generation 74181 ALU § Hi function : 16 patterns Computer Systems Lab. YONSEI UNIVERSITY 33

Segment l Pattern Generation 74181 ALU § § § 74181 ALU : N 2 Hi = (Ai X Bi)’ Li = Ai’ Design constraints : Hi. Li = 01 is impossible 34 AB tests X 22 M Cn tests : 324 Segment Test : 324 + 16 = 356 Computer Systems Lab. YONSEI UNIVERSITY 34

Pseudo Exhaustive Pattern Generation l 8 input parity tree l Instead of 256 pattern, only 4 patterns are required § § § Minimum pseudo exhaustive pattern a b c d e f g h i j k l m n 0 0 0 0 1 1 1 1 0 1 0 1 1 1 0 0 1 1 0 Computer Systems Lab. YONSEI UNIVERSITY 35

Constant Weight Pseudo Exhaustive l Pattern Generation Any (n, w) circuit can be tested by a constant weight counter implementing a w-out-of-k code for an appropriate value of k § n : number of inputs § w : weights Ämaximum of inputs for any cone l 2 -out-of-4 code § § § 1100 1010 1001 0110 0101 0011 Computer Systems Lab. YONSEI UNIVERSITY 36

Pseudo Random Pattern l Pattern Generation Test Pattern Source § ALFSR (Autonomous Linear Feedback Shift Register) LFSR § All patterns equally likely § Sometimes misnamed random Computer Systems Lab. YONSEI UNIVERSITY 37

Random vs Pseudorandom l Pattern Generation Random § Patterns can occur more than once § Non-reproducible l Pseudorandom § All (possibly except all-0 pattern) patterns occur before any pattern repeats § Reproducible Computer Systems Lab. YONSEI UNIVERSITY 38

Linear Feedback Shift Register l Pattern Generation The state of shift register depends only on the prior state Computer Systems Lab. YONSEI UNIVERSITY 39

Linear Feedback Shift Register l Pattern Generation Polynomial § shorthand notation for a bit stream l x 6+x 2+x+1 § 1000111 § 1 X 6+0 X 5+0 X 4+0 X 3+1 X 2+1 X+1 l Arithmetic of polynomial is modulo 2 § Addition and subtraction is the same § (x-1) is the same as (x+1) l Degree of a polynomial is the highest power of the nonzero term Computer Systems Lab. YONSEI UNIVERSITY 40

Linear Feedback Shift Register l Pattern Generation Generating function G(x) § G(x) = a 0+a 1 x+a 2 x 2+…+amxm+. . . = amxm where ai is 0 or 1 l For type 1 LFSR § Computer Systems Lab. YONSEI UNIVERSITY 41

Linear Feedback Shift Register l Pattern Generation Characteristic polynomial P(x) § P(x) = 1+c 1 x+c 2 x 2+…+cnxn l If a-1=a-2=…=a 1 -n=0 and a-n=1 then Computer Systems Lab. YONSEI UNIVERSITY 42

Linear Feedback Shift Register l Pattern Generation Maximum length sequence § Period of 2 n-1 for n stage LFSR § Disregard all 0's l Primitive polynomial § Characteristic polynomial with a maximum length sequence l Non Primitive Polynomial § Less than maximal length l Irreducible polynomial § Not divisible by any other polynomial other than 1 and itself § Has an odd number of terms including the 1 term § If its degree n is greater than 3, the P(x) must divide into 1+xk where k = 2 n-1 § Example Äx 4+x 3+1 divides evenly into X 15+1 Computer Systems Lab. YONSEI UNIVERSITY 43

Linear Feedback Shift Register l Pattern Generation Number of Primitive Polynomials § § § § § n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PPs 1 1 1 2 6 6 18 16 48 60 176 144 630 756 1800 2048 Computer Systems Lab. n 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PPs 7710 7776 27594 24000 84672 120032 356960 276480 1296000 1719900 4202496 4741632 18407808 17820000 69273666 67108864 YONSEI UNIVERSITY 44

Linear Feedback Shift Register l Pattern Generation Primitive Polynomial § § § § n 1, 2, 3, 4, 6, 7, 15, 22 5, 11, 29 10, 17, 20, 25, 28, 31 9 23 18 8 12 13 14, 16 19, 27 24 26 30 32 Computer Systems Lab. Primitive Polynomial 1+x+xn 1+x 2+xn 1+x 3+xn 1+x 4+xn 1+x 5+xn 1+x 7+xn 1+x 2+x 3+x 4+xn 1+x+x 4+x 6+xn 1+x+x 3+x 4+xn 1+x 3+ x 4+x 5+xn 1+x+x 2+x 7+xn 1+x+x 2+x 6+xn 1+x+x 23+xn 1+x+x 22+xn YONSEI UNIVERSITY 45

Linear Feedback Shift Register l Pattern Generation Pseudo Random Pattern Generation § § § Characteristic Polynomial : 1+x 2+x 3 Initial condition (1, 0, 0) : x Q 1 : x / (1+x 2+x 3) Q 2 : x 2 / (1+x 2+x 3) Q 3 : x 3 / (1+x 2+x 3) Computer Systems Lab. YONSEI UNIVERSITY 46

Linear Feedback Shift Register l Pattern Generation When initial state is 100 § § § Q 1 Q 2 Q 3 1 0 0 0 1 0 1 1 0 0 0 1 0 1 Computer Systems Lab. YONSEI UNIVERSITY 47

Linear Feedback Shift Register l Pattern Generation When initial state is 000 § Q 1 Q 2 Q 3 § 0 0 0 Computer Systems Lab. YONSEI UNIVERSITY 48

Combined LFSR and SR l Pattern Generation Less cost than constant weight counter Computer Systems Lab. YONSEI UNIVERSITY 49

Combined LFSR and XOR l Pattern Generation Close to LFSR/SR § Q 1 Q 2 Q 3 Q 4 § 1 0 0 1 § 0 1 0 0 § 1 1 § 0 1 1 0 § 0 1 § 0 0 1 1 § 1 0 0 1 Computer Systems Lab. YONSEI UNIVERSITY 50

Condensed LFSR l l Pattern Generation Efficient when w >= n/2 When w < n/2, use combined LFSR and SR Computer Systems Lab. YONSEI UNIVERSITY 51

Cyclic LFSR l l Pattern Generation When w < n/2 Condensed LFSR § Produce long test length for (n, w) circuits l Combined LFSR and XOR § Have a high hardware overhead l l Use cyclic code Low hardware overhead and reduce test length Computer Systems Lab. YONSEI UNIVERSITY 52

LFSR for Exhaustive Test l Pattern Generation Include NORs Computer Systems Lab. YONSEI UNIVERSITY 53

Weighed Random Patterns l l Pattern Generation All patterns not equally likely Pseudo random test patterns are inefficient when randompattern-resistant faults exist. Make Prob[1] Prob[0] at pattern sources Random resistant faults § Consider a 32 input AND and output s-a-1 fault § The output s-a-1 is detected when all inputs are 1 § When pseudo random testing is used, the detection probability is 1/232 Computer Systems Lab. YONSEI UNIVERSITY 54

WRPG l l l Let pf be the detection probability of fault f (1 - pf)N : probability that f is not detected by N independent patterns C = 1 -(1 - pf)N : Confidence of detecting f by a random test set of N patterns. N = ln(1 -C)/ln(1 - pf) : # of patterns to reach Confidence C. The test length required for detecting a set of faults F only depends on the fault f with the lowest detectability. Example> 32 -input AND gate § Pseudo random testing Ä4. 48 X 1010 patterns required to reach C = 0. 999 § WPRG ÄWhen the probability of 0 is 1/232 Äpf = 0. 5, N=600 Computer Systems Lab. YONSEI UNIVERSITY 55

Multiple Weight Sets l l l Consider a circuit with a 32 input AND and a 32 input OR where the same 32 inputs feed them Consider AND output s-a-1 and OR output s-a-0 If the same weights applied, one of two faults are hard to detect. It is necessary to have 2 different weight sets (1/232, 1 -1/ 232) (1 -1/ 232, 1/ 232) Computer Systems Lab. are YONSEI UNIVERSITY 56

Multiple Weight Sets l l The efficiency of multiple weight set is determined by both the number of weight sets (r), and the total number of random test patterns to be applied (N). The goal of weight generation is to reduce both r and N Computer Systems Lab. YONSEI UNIVERSITY 57

Multiple Weight Sets l Single weight set § Advantage ÄSmall hardware overhead § Disadvantages ÄLow fault coverage ÄLong test pattern length l Multiple weight sets § Advantages ÄHigh fault coverage ÄShort test pattern length § Disadvantages ÄLarge hardware overhead Computer Systems Lab. YONSEI UNIVERSITY 58

Weight Generation Methods l Structural analysis § Small number of patterns and weight sets § Easy implementation § Poor fault coverage l Deterministic test sets § All non-redundant faults can be detected § A high number of random patterns and weights § Large hardware overhead l Combined both methods Computer Systems Lab. YONSEI UNIVERSITY 59

Maximizing Don’t Cares l If “Don’t Cares” occur in a test set they must not contribute to the weights Äby maximizing the number of “Don’t Care” bits , ATPG can remove redundancies in the test set Computer Systems Lab. YONSEI UNIVERSITY 60

Maximizing Don’t Cares l l l Decisions are guided by a number of heuristics which particularly aim at generating test patterns with a large number of unspecified bits, and keeping the overall test set small For error propagation, a node on the D-frontier is selected which is as close as possible to the POs and is located on a path with a maximum number of undetected faults, For line justification, observability are used if there is a choice of a gate input line to be set to a controlling value § if the gate output is observable Äa gate input line is selected such that the number of undetected faults preceding this line is maximum § if not observable Äa gate input line is selected such that the number of primary inputs to be set becomes minimal Computer Systems Lab. YONSEI UNIVERSITY 61

ATPG and Weight Generation A) ATPG is performed for all the undetected faults. ATPG tries to maximize the number of “Don’t Cares” B) Weight generation C) WRPG and fault simulation. Pattern generation is stopped if the last k successive patterns do not detect any new fault. ( k = a user-defined parameter) B’) Weight computation by using Hamming distance § Resolving conflicts U ÄOnly the patterns from D(t, T, m) are used for weight generation reversing weight generation Computer Systems Lab. YONSEI UNIVERSITY 62

Comments l l Pseudo Random Test Pattern could be proved to be inefficient when Random-pattern-resistant faults exist. Weight set generation methods can be based on the structural analysis or deterministic test sets. If possible, the small number of weight sets, the small number of total test patterns, and High fault coverage should be achieved at the same time. To combine advantages of both methods, Weight generation and ATPG could be integrated. § Maximize the number of “Don’t Cares” in deterministic sets. § Resolving conflict information problem by partitioning deterministic test patterns l l in actually testing , WRP is generated by circuits consisting of LFSR and combinational logic. Rounding of weights Computer Systems Lab. YONSEI UNIVERSITY 63

Response Analysis l l l Response Analysis Duplication Ones Count Transition Count Parity Check Syndrome Signature Analysis Computer Systems Lab. YONSEI UNIVERSITY 64

Duplication l l Response Analysis Comparison of outputs of 2 implementations Can avoid alias problem Can avoid loss of effective fault coverage of a signature analyzer Hardware overhead Computer Systems Lab. YONSEI UNIVERSITY 65

Compression l l Response Analysis Signature : output of the compactor Decision factors § § Extra hardware Loss of fault coverage Calculation of good signature Aliasing ÄA faulty circuit produces a signature that is identical to the signature of a fault free circuit Computer Systems Lab. YONSEI UNIVERSITY 66

Ones Count l l l Response Analysis Count the number of ones at the output After applying n vectors, the signature is between 0 and n Masking probability § Prob(masking) = ( n. Cp - 1 ) / (2 n - 1) Computer Systems Lab. YONSEI UNIVERSITY 67

Transition Count l Response Analysis Signature § The number of 0 -to-1 and 1 -to-0 transitions at the output l l After applying n vectors, signature is between 0 and n-1 Masking probability § Prob(masking) = 2 X (n-1)Cp / (2 n-1) § p : the number of transitions in a fault free response Computer Systems Lab. YONSEI UNIVERSITY 68

Parity Check l l Response Analysis Signature : parity Compression circuit consists of a XOR and a D FF § LFSR with G(x) = x + 1 l Masking probability § Prob(masking) = ( 2(n-1) - 1 ) / (2 n - 1) Computer Systems Lab. YONSEI UNIVERSITY 69

Syndrome l l Response Analysis All 2 n patterns are applied to the input The number of 1's at an output is counted Compare the number of 1's for good machine and for faulty machine Syndrome S = k/2 n § k : the number of minterms § n : the number of inputs § Normalized number of ones at the output l l Not all Boolean functions are totally Syndrome testable Used for exhaustive testing Computer Systems Lab. YONSEI UNIVERSITY 70

Syndrome l No reconvergent fanout § § § l Response Analysis C 3 AND NAND OR NOR XOR Syndrome of S 3 S 1 S 2 1 - S 1 S 2 S 1 + S 2 - S 1 S 2 1 - ( S 1 + S 2 - S 1 S 2) S 1 + S 2 - 2 S 1 S 2 Reconvergent fanout § § C 3 AND OR XOR Syndrome of S 3 S 1 + S 2 + S((FG)’) - 1 S 1 + S 2 - S(FG) S( F’G) + S(FG’) Computer Systems Lab. YONSEI UNIVERSITY 71

Signature Analysis l l Response Analysis Compaction of Test Data in a LFSR How to compare the results? § Applying test sequence and compare signature l Signature § value left in LFSR l l To obtain signature and initialization pattern, use a golden board Aliasing § Fault free signature is the same as fault signature § Probability : 1/2 n Computer Systems Lab. YONSEI UNIVERSITY 72

Signature Analysis Computer Systems Lab. Response Analysis YONSEI UNIVERSITY 73

Signature Analysis l Response Analysis Initial Value : 000 § § § Good Patterns Z 1 Z 2 Z 3 1 1 0 0 1 0 Computer Systems Lab. Good Responses Q 1 Q 2 Q 3 1 1 0 1 Faulty Patterns Z 1 Z 2 Z 3 1 1 0 0 1 1 Faulty Responses Q 1 Q 2 Q 3 1 1 0 0 1 1 YONSEI UNIVERSITY 74

Aliasing l Response Analysis Initial Value : 000 § § § Good Patterns Z 1 Z 2 Z 3 1 1 0 0 1 0 Computer Systems Lab. Good Responses Q 1 Q 2 Q 3 1 1 0 1 Faulty Patterns Z 1 Z 2 Z 3 1 0 0 0 1 1 Faulty Responses Q 1 Q 2 Q 3 0 1 1 1 0 1 YONSEI UNIVERSITY 75

Aliasing l l l Response Analysis For the register length n and the length of test bit stream m, assume that all possible bit streams are evenly distributed over all possible signatures The number of bit stream that produce a specific signature is 2 m/2 n = 2 m-n For a particular fault-free response, there are 2 m-n -1 erroneous bit stream with same signature Since there a total of 2 m-1 possible erroneous response streams, the aliasing probability is (2 m-n-1)/(2 m-1) = 2 -n Reduce aliasing § Increase the length of register chain § Access signature several times Computer Systems Lab. YONSEI UNIVERSITY 76

Signature Analysis l Response Analysis Parallel § Faster l Serial Computer Systems Lab. YONSEI UNIVERSITY 77

MISR l l Response Analysis Normally, a single input signature analyzer is not used due to testing overhead Aliasing Probability : 1/2 n § All error patterns are equally likely Computer Systems Lab. YONSEI UNIVERSITY 78

Using ALU l Response Analysis Low Overhead Computer Systems Lab. YONSEI UNIVERSITY 79

Alias Probability l l l Response Analysis P (fault not detected) = P(no output error) + P(output error | correct signature) P (fault not detected) = P(no output error) + P(output error) P(correct signature | output error) P (no output error) § escape probability l P (correct signature output error ) § alias probability (PAL) Computer Systems Lab. YONSEI UNIVERSITY 80

PAL l Response Analysis Depends on § P : characteristic of fault and circuit § L : test length § f(x) : polynomial describing signature register l l Exact calculation of PAL is NP-complete Bound for Serial Signature Analysis § § l PAL <= (1+e)/L if L < Lc PAL <= 1 if L = h X Lc PAL <= 2/(L 2+1) if L>Lc and L h X Lc Lc Äsignature register period Ämaximum autonomous cycle length What we want § Alias probability upper bound, independent of P l Use signature polynomial with period test length Computer Systems Lab. YONSEI UNIVERSITY 81

BIST Structures Architectures l On-line BIST § Testing occurs during normal operating conditions § Self checking l Off-line BIST § Embedded ÄUse system registers to generate and compact test data § Separate ÄUse registers external to the system function to generate and compact test data § Centralized ÄSeveral CUTs share TPG and ORA § Distributed Computer Systems Lab. YONSEI UNIVERSITY 82

BIST Structures l Architectures Decision factors § § § § Degree of test parallelism Fault coverage Level of packaging Test time Physical constraints Complexity of replaceable units Performance degradation Computer Systems Lab. YONSEI UNIVERSITY 83

Separate BIST l Architectures Drawbacks § Long test time § Poor delay l Advantages § Low overhead § Simple control logic l Danger § Decimation Dependency § Linear Dependency Computer Systems Lab. YONSEI UNIVERSITY 84

Decimation Dependency l Architectures The number of LFSR patterns, M § 2 m or 2 m-1 l The number of possible different scan path patterns, P § Minimum of the followings ÄM ÄN=2 n Ä( LCM of M and n )/n = M / (GCD of M and n) l Example § m=4, M=15, n=5 : P=3 § m=10, M=1023, n=9 : P=341 Computer Systems Lab. YONSEI UNIVERSITY 85

Linear Dependency l Architectures If n < m § No linear dependency l If n >= m and kj >= m § Possible linear dependency Computer Systems Lab. YONSEI UNIVERSITY 86

CSBL l Architectures Centralized and separate board level BIST § No boundary scan § Best suited for not many feedbacks § Fault simulation is required to determine the number of test vectors to achieve an adequate level of fault coverage Computer Systems Lab. YONSEI UNIVERSITY 87

LOCST l Architectures LSSD On-Chip Self Test § § Centralized and separate BIST Scan path (LSSD) Boundary scan On-chip test controller Computer Systems Lab. YONSEI UNIVERSITY 88

STUMPS l Architectures Self Testing Using MISR and Parallel SRSG § Centralized and separate BIST § Multiple scan paths ÄReduction in test time § No boundary scan l Lower overhead than BILBO but takes longer to apply Computer Systems Lab. YONSEI UNIVERSITY 89

CBIST l Architectures Concurrent BIST § § Centralized and separate BIST No scan or boundary scan Can be used for sequential logic On-line testing ÄPRPG and MISR are initialized until Enable signal is enabled § Off-line testing ÄPRPG drives the circuit and responses are compressed in MISR Computer Systems Lab. YONSEI UNIVERSITY 90

CEBS l Architectures Centralized and Embedded BIST with Boundary Scan § The first r bits of the input boundary scan registers are used for PRPG and the last s bits are used for MISR or SISR Computer Systems Lab. YONSEI UNIVERSITY 91

Random Test Data l l Architectures Distributed and embedded BIST Boundary scan Some binary patterns are repeated Others may not be generated § R 1 and R 2 : PRPG § R 2 and R 3 : MISR Computer Systems Lab. YONSEI UNIVERSITY 92

Simultaneous Self-Test l Architectures Distributed and embedded BIST § Scan path § No LFSR § No boundary scan l l Problem in testing external logic Problem in characterizing the quality of test process Computer Systems Lab. YONSEI UNIVERSITY 93

Simultaneous Self-Test l Architectures Use self-test storage cell for each storage cell § Normal mode : Q = D § Test mode (self test) : Q = D Si ÄTest Mode=1 § Scan mode ÄTest Mode=0 Computer Systems Lab. YONSEI UNIVERSITY 94

Cyclic BIST l Architectures Use sequential circuits as nonlinear binary sequence generators § If there are more outputs than inputs, extra outputs can be combined using XOR § Low area overhead § Effectiveness is circuit dependent § Asynchronous feedbacks are possible § CUT should be clocked a predetermined times (determined by fault simulation) Computer Systems Lab. YONSEI UNIVERSITY 95

Circular BIST l Architectures General architecture § § § Register based Partial self test All inputs and outputs must be associated with boundary scan cell All storage cell must be initializable before testing LFSR with primitive polynomial 1+xn Computer Systems Lab. YONSEI UNIVERSITY 96

Circular BIST l l Architectures Storage Cell [A] § N/T Z Mode § 0 Dj System § 1 Dj Sj-1 Test l l [B] § § § B 0 B 1 0 0 0 1 1 Z 0 Sj Dj Dj Sj-1 Computer Systems Lab. Mode Reset Scan System Test YONSEI UNIVERSITY 97

Circular BIST l Architectures Test process § Initialization § Testing of circuit § Response evaluation Computer Systems Lab. YONSEI UNIVERSITY 98

Circular BIST l Architectures Advantages § High fault coverage § Low hardware overhead § One test per clock l Disadvantages § Pattern generation is heavily dependent of the circuit function § Certain pattern may be generated § May be used with partial scan path to apply deterministic patterns Computer Systems Lab. YONSEI UNIVERSITY 99

Scan Dependence l l Architectures Possible if use output of MISR as test patterns FF (i+1) is scan dependent iff during normal operation it is functionally dependent on the previous FF(i) in the scan path Computer Systems Lab. YONSEI UNIVERSITY 100

Scan Dependence l Architectures Example § Normal mode : Zi+1 = Qi + f § MISR mode : Zi+1 = Qi’f : incorrect l l l Yi+1 is scan dependent if Yi+1 is a function of Yi Eliminate scan dependence by reordering scan path Use scan dependence to reduce BIST overhead § Redesign scan cell for scan dependence bits Computer Systems Lab. YONSEI UNIVERSITY 101

BILBO(Built-In Logic Block Observer) l Architectures Take advantage of the register aspects of many design § Program counter, instruction register, accumulator l l l Normal registers are replaced by BILBO register Inputs to a logic C are driven by a BILBO register Output of C drives another BILBO register Computer Systems Lab. YONSEI UNIVERSITY 102

BILBO(Built-In Logic Block Observer) § § § B 1 1 0 0 1 Architectures B 2 Mode 1 Normal Mode 1 Reset 0 Shift Register 0 Signature Analyzer Computer Systems Lab. YONSEI UNIVERSITY 103

BILBO Operations l Architectures Shift Register Mode : B 1=B 2=0 Computer Systems Lab. YONSEI UNIVERSITY 104

BILBO Operations l Architectures Normal Mode : B 1=B 2=1 Computer Systems Lab. YONSEI UNIVERSITY 105

BILBO Operations l l Architectures Signature Analysis Mode : B 1=1 B 2=0 If Z 1=Z 2= … =Zn=0, PRPG Computer Systems Lab. YONSEI UNIVERSITY 106

BILBO l Architectures To test A § R 1 : RPG § R 2 : Signature Analyzer l To test B § R 2 : RPG § R 1 : Signature Analyzer Computer Systems Lab. YONSEI UNIVERSITY 107

Bus Oriented BILBO l Architectures In PRPG mode, BILBO register need to be held at constant value by disabling all bus drivers and using pull-up or pull -down circuitry Computer Systems Lab. YONSEI UNIVERSITY 108

BILBO Pipeline l Architectures Need to deactivate inputs to BILBO registers during PRPG mode Computer Systems Lab. YONSEI UNIVERSITY 109

BILBO l Architectures Advantages § At-speed test § Reuse system bistables l Drawbacks § Multiple Test sessions § Complex control l Danger § Register self-adjacency Computer Systems Lab. YONSEI UNIVERSITY 110

Register Self-Adjacency l l l Architectures A register Ri is said to be a driver of a logic C if some outputs of Ri are inputs to C A register Rj is said to be a receiver of C if some outputs if C are inputs to Rj Ri is said to be adjacent to Rj if there exists a block of logic C such that Ri is a driver of C and Rj is a receiver of C If Ri is both a receiver and a driver of C, it is self-adjacent Avoid by design or synthesis Use Concurrent BILBO Computer Systems Lab. YONSEI UNIVERSITY 111

Concurrent BILBO l Architectures Register can be operated as PRPG and MISR simultaneously § § B 1 1 0 B 2 0 1 1 Mode Normal Scan PRPG/MISR Computer Systems Lab. YONSEI UNIVERSITY 112

Test Schedule l Architectures Test session § An assignment of test modes to BILBO registers to test one or more blocks l Test scheduling problem § Determine the minimal number of test sessions required to test all blocks of combinational logic § Determine the minimal colors that can be assigned to the nodes of a graph such that no edge connects two nodes of the same color l More complex when the test time for each block is considered Computer Systems Lab. YONSEI UNIVERSITY 113

Partial BILBO Pipeline l l Architectures Only a subset of registers are made for BILBO Reduction on hardware complexity Computer Systems Lab. YONSEI UNIVERSITY 114

Control of BILBO l Architectures When multiple test sessions exist, the efficient control becomes important § The first cell of BILBO register and the control lines to all the cells are driven by the above logic § S* drives the S 0 to the first cell in BILBO register § T 0 T 1 T 2 Mode B 0 B 1 S* § 1 0 0 PRPG 0 1 FB § 1 0 1 MISR 1 1 FB § 0 0 Q SHIFT 0 1 Q § 1 1 X LATCH 1 0 X § 0 1 1 RESET 0 0 X Computer Systems Lab. YONSEI UNIVERSITY 115

Control of BILBO l Architectures Control Sequence § § § Inhibit system clocks and enter the test mode Initialize control registers with data specific to a test session Send the LFSRs and scan paths Initiate the test process Process the final signature to determine if an error has been detected Computer Systems Lab. YONSEI UNIVERSITY 116

STARBIST l l Architectures Each cluster contains one parent test vector in the center A number of children patterns is derived from parent test vector by complementing certain number of coordinates in pseudo-random pattern This method doesn’t use the conventional LFSR directly to generate pseudo-random patterns The implementation makes use of scan order and polarity between the neighboring scan cells Computer Systems Lab. YONSEI UNIVERSITY 117

Phase Shift BIST l Architectures Partition circuit into NAC and scan chain § NAC(Nearly Acyclic Circuit) Äsequential synchronous circuit the period of which is not larger than 1 l Pseudo random patterns by LFSR and PS are applied through primary inputs and scan chain § PS(Phase Shifter) Ärequired to avoid the structural dependency between outputs of pattern generator l Compress output values using MISR and SC(Space Compressor) Computer Systems Lab. YONSEI UNIVERSITY 118

Phase Shift BIST Computer Systems Lab. Architectures YONSEI UNIVERSITY 119

Multiple Fixed Biased PR BIST l l Architectures Pattern is applied to CUT (Circuit Under Test) through n idler register segment Idler register segment is operated by BIST pattern generation and control logic Each idler register segment has a different biasing value and some bits are fixed to a specified value The output of CUT is passed to MISR and fault identification is performed using signature that remains in MISR Computer Systems Lab. YONSEI UNIVERSITY 120

Multiple Frequency Scan BIST l l l Architectures Several scan chains is synchronized in different frequencies Each frequency is generated by system clock and primary inputs To synchronize different scan chains, clock number required to load scan chain and perform sampling must be divided by the ratio of any frequency pair BIST core is composed of random pattern generator, signature analyzer, pattern counter, scan mode signal generator, and clock generator Better performance than STUMPS Computer Systems Lab. YONSEI UNIVERSITY 121

Multiple Frequency Scan BIST Computer Systems Lab. Architectures YONSEI UNIVERSITY 122

Conclusion l Conclusion In BIST, the test pattern generation and the output response evaluation are done on chip § The use of expensive ATE machines to test chips can be avoided. l Requirements of a BIST scheme § Easy to implement § Small area overhead § High fault coverage l Advantage § No need for expensive tester § At-speed testing Computer Systems Lab. YONSEI UNIVERSITY 123