Buffering To Drive large load special buffers capable

Buffering To Drive large load, special buffers capable of delivering current at high speed are essential. u Load may be on-chip such as the clock distribution network or off-chip such as the pad drivers. u u. An effective way to minimize large capacitive load is to implement a Tapered Buffer that is a chain of inverters with a gradual increase in driving capability Buffer Large Load • The Objective: Given a load capacitance, CL design a scaled (tapered) chain of N inverters such that the delay time between the logic gate and the load capacitance node is minimized u. The task is to determine: number of stages (N) and the tapering factor (S) 1

OUTPUT Pad and Driver 2

CLOCK DRIVER 3

Buffering S = scaling or tapering factor CL = SN+1 Cg ……………… All inverters have identical delay of to = delay of the first stage (load =Cd+Cg) 4

Buffering If the diffusion capacitance Cd is neglected, then S = e = 2. 7 5 S 4 3 0 1 2 3 Cd/Cg 5

Layout of a standard inverter Diffusion Polysilicon Metal Wp Vin PMOS Vo Wn L NMOS VSS 6

Layout of Large Device • Drain-Source Area • Delay of Gate 7

Layout of a Buffer D(rain) S Multiple Contacts D G S(ource) S G(ate) (a) small transistors in parallel (b) circular transistors 8 Prentice Hall/Rabaey

Large Transistor Layout Increase # of Contacts 9

Output Drivers Standard CMOS Driver Open Drain/Source Driver: Single Transistors Tri-state Driver Bi-directional Circuit 10

Output Drivers Bonding Pad GND 100 mm Out VDD In GND 11 Prentice Hall/Rabaey

Tri-state Driver u u u Tri-state or High impedance Used to drive internal or external busses Two inputs: Data In and Enable Various signal assertions Two types: In C 2 MOS CMOS with Control Logic VDD En Out En C 2 MOS 12

Tri-state Driver VDD Control logic could be modified to obtain En Inversion/non-inversion Active low/high Enable Out For large load, pre-drivers are required PAD En In 13

Latch-up on CMOS Inherent in bulk CMOS processes are parasitic bipolar transistors forming p+/n /p /n+ path between VDD and VSS The four layer path is equivalent to SCR which when triggered can cause self sustaining latch-up between power supplies resulting in total or local destruction. VDD VSS n+ p+ p+ n+ T 1 Rw P-well Rs n+ T 2 VDD p+ Rs T 2 Drain of PMOS Drain of NMOS T 1 Rw n-substrate Vss 14

Latch-up: Analysis If VA>VDD+0. 6, T 1 will be turned ON u Ic 1 causes a voltage drop across Rw u If V(Rw) > 0. 6 V V, T 2 will be turned ON, this forces Ic 2 to be supplied by VDD through n+ substrate contact, then the bulk to p-well. u Increase in voltage across Rs causes and in increase in Ic 1, hence sustaining SCR action. u The same action will take place when: VB< -0. 6 V u Hence to prevent latch-up, limit the output voltage -0. 6< Vout < VDD+0. 6 V u VDD IE 1 Rs IB 1 IC 1 VA T 1 IC 1 T 2 IB 2 VB Rw IE 1 VSS 15

Latch-up: Trigger Factors which trigger latch-up u u u u transmission line reflections or ringing voltage drop on the VDD bus “hot plug in” of unpowered circuit board electrostatic discharge sudden transient on power and ground busses leakage current across the junction radiation: x-ray, cosmic 16

Latch-up: Prevention 1. Layout techniques: Incorporate collectors for latch-up current: Create diffused n and p guard rings that surround active devices These collectors can sink the current but are incapable of sustaining the latch-up mechanism once the cause is removed guard ring n+ p+ n+ n+ p+ p+ n+ p+ GND 17

Input protection u. Electrostatic discharge can take place through transfer of charges from the human body to the device. u. Human body can carry up to 8000 V. u. Discharge can happen within hundreds of nanoseconds. u. Critical field for Si. O 2 is about 7 X 106 V/cm. u. For 0. 5 u CMOS process the gate oxide can withstand around 8 V u. Some protection technique is required with minimum impact on performance 1 M 1. 5 K Vesd DUT 100 p. F Human Body model 18

Input PAD 19

Protection Circuitry Principles Punch Through Avalanche 20

Vd d Input Pad Circu it Vs s 21

ESD Structures Basic technique is to include series resistance and two clamping diodes. The resistance R is to limit the current and to slow down the high voltage transitions. R could be polysilicon or diffusion resistance Diffusion resistance could be part of the diode structure Typical values of R: 500 to 1 k VDD R PAD 22

Protection Circuitry Based on gate modulated junction breakdown 23

Protection Circuitry 24

Layout of ESD Structure This structure uses transistors as clamping diodes PAD n+ p+ Guard Ring p+ p+ n+ n+ 25

Layout of ESD Structure VDD PAD n+ p+ Guard Ring p+ p+ n+ n+ GND 26

VDD Guard Rings for critical Transistors Vin Diffusion n+ N Contact Polysilico Vss n Diffusion P+ Metal 27

VDD 28

Structure of a P+ Diode VDD N+ Guard N Sub M 1 P+ Input OUTPUT 29

Another ESD Structure VDD PAD R 1 R 2 Thick FOX MOS Transistor 30

Bi-direct PAD VDD Pre-drivers IN ESD Protection Control Logic EN Input Buffer PAD 31

D 2 D 3 R PAD D 1 D 2 D 3 D 1 D 4 R N+ P substrate P+ N-Well Si. O 2 N+ @ VDD connected to Gnd 1 X D 4 Metal– to CCT 4 X

2 D vs. 2. 5 D vs. 3 D ICs 101 By: Clive Maxfield 4/8/2012 12: 08 PM EDT Birds-eye view of circuit board with individually packaged chips Birds-eye view of circuit board with a System-in-Package (Si. P) device Birds-eye view of circuit board with a System-on-Chip (So. C) device Birds-eye view of circuit board with a System-in-Package (Si. P) device 33

3 D Structures 2 D vs. 2. 5 D vs. 3 D ICs 101 By: Clive Maxfield 4/8/2012 12: 08 PM EDT A simple form of 3 D IC/Si. P Connecting dice using wires running down the sides 3 D stack A more complex “True 3 D IC/Si. P A simple “True 3 D IC/Si. P” 34

Thank you ! 35