Buffering Clock Signals 1 Clock signals generated from

Buffering Clock Signals (1) Clock signals (generated from VCO or clock divider) often drive large capacitive loads. 1 x C … 1 x n 1 x C C Fanout = n For a large fanout, attenuation of clock amplitude will occur. EECS 270 C / Winter 2016 Prof. M. Green / U. C. Irvine 1

Buffering Clock Signals (2) ktp 1 x nx kx k 2 x … m stages Now is increased by k << n less attenuation at each stage Delay = mktp Power = P 1(1 + k 2 + … + n) Power dissipated by first stage As fclock 1/tp then k 1; number of stages and total power become very large. EECS 270 C / Winter 2016 Prof. M. Green / U. C. Irvine 2

Buffering Clock Signals (3) Since clock signal is made up of a single frequency (+ harmonics), resonance can be used to increase gain with greatly reduced power dissipation. Resonant frequency: at resonance If lossless inductors were available, we could achieve high gain at any frequency simply by choosing the correct inductor value. EECS 270 C / Winter 2016 Prof. M. Green / U. C. Irvine 3

On-Chip Passive Elements l Resistor: l t w l Capacitor: l w (+ fringing) d substrate l Inductor: t w l l l p. H/ m Inductance calculation much more complicated! EECS 270 C / Winter 2016 Prof. M. Green / U. C. Irvine 4

l t l l l p. H/ m w Special case of Greenhouse result Note for l >> w, L is a weak function of w To increase effective inductance per unit length, we make use of mutual inductance via spiral structure: EECS 270 C / Winter 2016 Prof. M. Green / U. C. Irvine 5

Modeling of Spiral Inductor 1 2 Accurate lumped model should include: • Series inductance (self + mutual) & resistance • Skin effect (frequency dependent series resistance) • Interwinding capacitance • Capacitance to substrate • Substrate capacitance & loss number of turns n = 2 Design of inductor requires: • inductor simulation package (e. g. , asitic) • trial and error • conversion to lumped element model EECS 270 C / Winter 2016 Procedure for constructing lumped model: 1. 2 -port s-parameters over frequency range of interest (this comes from the inductor simulator) 2. Choose lumped circuit topology. 3. Run simulations to find the optimal lumped circuit element values such that the circuit s-parameters are sufficiently close to the inductor’s s-parameters (can use. net and. optimize in HSPICE) Prof. M. Green / U. C. Irvine 6

Modeling of Spiral Inductor (cont. ) Link to “asitic” web pages: http: //rfic. eecs. berkeley. edu/~niknejad/asitic. html Inductor magnitude impedance vs. frequency Parameters most relevant to circuit designers: • Inductance • Series resistance • Self-resonant frequency EECS 270 C / Winter 2016 Prof. M. Green / U. C. Irvine 7

Modeling of Spiral Inductor (cont. ) Cint 1 1 2 L Cox 1 2 Rsub 1 Csub 1 L: Rs: Cint: Cox: Csub/Rsub: Rs Cox 2 Csub 2 Rsub 2 Self/mutual inductance Series resistance Interwinding capacitance Oxide capacitance Substrate capacitance/resistance Values of L and Rs in lumped model should correlate with physical parameters. Values of other lumped model elements need not necessarily correlate with physical parameters. EECS 270 C / Winter 2016 Prof. M. Green / U. C. Irvine 8

Parasitic capacitances usually combine with load capacitance L should be decreased slightly Series Rs has more important effect: L C R L' C R’ Rs At resonance, Im [Y(j r)] = 0: Slight increase in effective inductance EECS 270 C / Winter 2016 Very important effect! Prof. M. Green / U. C. Irvine 9

CML Tuned Amplifiers (1) Differential-mode ground Sets common-mode output voltage CL resonates out with L Gain at resonant frequency = gm R’ EECS 270 C / Winter 2016 Prof. M. Green / U. C. Irvine 10

CML Tuned Amplifiers (2) Symmetric inductor structure can be used: Single structure allows more inductance to be realized from mutual coupling less series resistance EECS 270 C / Winter 2016 Prof. M. Green / U. C. Irvine 11

CML Tuned Amplifiers (3) Higher-gain topology: Gain is much higher at resonance, but depends completely on Rs. Variation in gain correlates with variation in metal (not resistor) sheet resistance. EECS 270 C / Winter 2016 Prof. M. Green / U. C. Irvine 12

CML Tuned Amplifiers (4) Watch out for ac current amplitude in inductors! Iin + IL Vswing L’ C R’ _ Let Vswing = 500 m. V, L=0. 5 n. H, f =10 GHz: Spiral inductor should be wide enough to meet ac electromigration specs. EECS 270 C / Winter 2016 Prof. M. Green / U. C. Irvine 13

Inductors in Broadband Circuits R LC lossless transmission line (Z 0) + R Vin 0. 5 Vout _ 0. 5 slope = -Td EECS 270 C / Winter 2016 Prof. M. Green / U. C. Irvine 14

Series Peaking (1) With direct connection of 2 buffers, output & input capacitances are in parallel: Cd Cg By connecting an inductor between the capacitors, the bandwidth and delay increase: Lser Cd Cg “Series peaking” EECS 270 C / Winter 2016 Prof. M. Green / U. C. Irvine 15

Series Peaking (2) R Using set Vx. Vin+ Vin- Lser Cd Vx+ Series peaking provides speed at the expense of extra delay. Cg Cd = Cg = 16 f. F R = 400 Frequency response: Lser = 0 BW = 6. 3 GHz Transient response: Vx (Lser = 3. 5 n. H) Lser = 3. 5 n. H BW = 8. 3 GHz Vx (Lser = 0) Vin Lser = 3. 5 n. H Lser = 0 EECS 270 C / Winter 2016 Prof. M. Green / U. C. Irvine 16

Shunt-Peaking (1) By connecting an inductor in series with the load resistor (series connection in shunt with output), more current is used, for a longer time, to charge the load capacitance. EECS 270 C / Winter 2016 Prof. M. Green / U. C. Irvine 17

Properties of Shunt-Peaking Frequency response: CL Resonant frequency: Im s X OX Re s L = 0: L ≠ 0: zero at s = −R/L pole at s = − 1/RC additional pole at s ≈ −(1/CR + R/L) EECS 270 C / Winter 2016 No resonance for Prof. M. Green / U. C. Irvine 18

Shunt-Peaking -- AC Response L = 1. 8 n. H BW = 9. 4 GHz Use of shunt-peaking increases small-signal bandwidth EECS 270 C / Winter 2016 BW = 6. 3 GHz Prof. M. Green / U. C. Irvine L = 3. 7 n. H BW = 14. 3 GHz 19

Shunt Peaking − Transient Response Step Response: Pulse Response (Dtin = 50 ps): L = 3. 7 n. H Dtout = 50. 8 ps ISI = 16 m. UI L = 3. 7 n. H td = 6. 7 ps L = 1. 8 n. H td = 8. 5 ps L = 1. 8 n. H Dtout = 50. 0 ps ISI = 0 m. UI L=0 Dtout = 48. 7 ps ISI = 26 m. UI td = 13. 4 ps EECS 270 C / Winter 2016 Prof. M. Green / U. C. Irvine 20

Shunt Peaking – ISI vs. Pulse Width ISI (UI) Input pulse width EECS 270 C / Winter 2016 Prof. M. Green / U. C. Irvine 21

Other Advantages of Shunt-Peaking • CML load is passive & linear • Can be shown to be very robust in the presence of parasitic series resistance and shunt capacitance inductors can be placed far away from other CML circuit elements. EECS 270 C / Winter 2016 Prof. M. Green / U. C. Irvine 22

Effect of Shunt-Peaking Inductor Parasitics (1) L L long metal lines L CP CP RP R R CL CL L RP R R CL CL • Series resistance RP simply adds to R • Shunt EECS 270 C / Winter 2016 capacitance CP resonates with L … Prof. M. Green / U. C. Irvine 23

Effect of Shunt-Peaking Inductor Parasitics (2) ISI (UI) Moderate amount of parasitic capacitance has similar effect to slightly larger inductor. Input pulse width ISI (UI) Disadvantages of using passive inductors: • Consume huge die area • Difficult to design & model EECS 270 C / Winter 2016 Prof. M. Green / U. C. Irvine Input pulse width 24

Multi-layer Inductors (1) metal 6 d metal 5 d Distance d between two metal layers is much smaller than lateral distances (e. g. , w, l, s) EECS 270 C / Winter 2016 Prof. M. Green / U. C. Irvine 25

Multi-layer Inductors (2) 2 -port representation of coupled inductors: i 1 _ i 1 i 2 + 1 series connection of coupled inductors: + + L 1 L 2 1 L 1 2 _ _ M + L 2 2 _ i 2 Passivity constraint: For metal geometries close to each other, k is close to unity. For L 1 = L 2 = L, we have: In general, for n layers we have: Multi-layer inductors are more appropriate for shunt-peaking than resonant structures due to additional contact resistance. EECS 270 C / Winter 2016 Prof. M. Green / U. C. Irvine 26

Multi-layer Inductors (3) Effective Capacitance: Ci Cj For more details, see: A. Zolfaghari, A. Chan & B. Razavi, “Stacked inductors and transformers in CMOS technology, ” IEEE Journal of Solid-State Circuits, vol. 36, April 2001, pp. 620 -628. EECS 270 C / Winter 2016 Prof. M. Green / U. C. Irvine 27

Multi-layer Inductors (4) Area comparison: metal 6 only 100 x 100 w = 4; s = 2; n = 4 L=2. 0 n. H R=6. 9 metal 6 over metal 4 46 x 46 w = 4; s = 2; n = 2. 5 L=2. 0 n. H R=12. 5 + EECS 270 C / Winter 2016 Prof. M. Green / U. C. Irvine 28

Active Inductors (1) Impedance inversion: Ideal gyrator: i 1 Rgyr i 2 iin + + + v 1 v 2 vin _ _ _ Matrix representation (Z-parameters): EECS 270 C / Winter 2016 Rgyr C Port 1 exhibits inductance when port 2 is connected to a capacitance. Prof. M. Green / U. C. Irvine 29

Active Inductors (2) Consider common-drain configuration: i 1 applied with port 2 open-circuited: i 2 RG + i 2 applied with port 1 open-circuited: v 2 _ _ i 1 (Assume RG gm > 1) v 1 + Complete Z-parameters (lossy/active gyrator): EECS 270 C / Winter 2016 Prof. M. Green / U. C. Irvine 30

Active Inductors (3) Interpretation of non-ideal matrix entries: + vin _ EECS 270 C / Winter 2016 Prof. M. Green / U. C. Irvine 31

Active Inductors (4) Impedance at port 1 with port 2 terminated with transistor Cgs: At low frequencies (Cgs open) Zsource = 1/gm At high frequencies (Cgs short) Zsource = RG EECS 270 C / Winter 2016 Prof. M. Green / U. C. Irvine 32

Active Inductors (5) Equivalent circuit: + vin _ EECS 270 C / Winter 2016 Prof. M. Green / U. C. Irvine 33

CML Buffer with Active Inductor Load Low-frequency gain: For shunt peaking: EECS 270 C / Winter 2016 Prof. M. Green / U. C. Irvine 34

Active Inductor AC Response RG = 4 k RG = 2 k RG = 0 EECS 270 C / Winter 2016 Prof. M. Green / U. C. Irvine 35

Active Inductor Transient Response (1) Differential signals: RG = 0 PW = 97 ps RG = 5 k PW = 100 ps EECS 270 C / Winter 2016 Prof. M. Green / U. C. Irvine RG = 10 k PW = 104 ps 36

Active Inductor Transient Response (2) Single-ended signals: Problem: n-channel load shifts output by Vt. Vsb > 0; body effects exacerbates this effect. . Single-ended input Single-ended outputs EECS 270 C / Winter 2016 Prof. M. Green / U. C. Irvine 37

Active Inductor Alternate Topology Alternate topology: p-channel load exhibits lower Vt (Vbs = 0) differential single-ended EECS 270 C / Winter 2016 Prof. M. Green / U. C. Irvine 38