BoundaryScan driven Vectorless Testing on Active Components Steve

Boundary-Scan driven Vectorless Testing on Active Components Steve Hird Loveland, CO BTW 2009

Purpose Describe a methodology that extends Boundary-Scan driven Vectorless test to include active components. BTW 2009 2

Outline • Review Existing technology used for connectors • Examine the unique challenges of active components • Examine some target devices • Conclusions BTW 2009 3

Using Boundary-Scan for Test Stimulus in VTEP test. • Combine Boundary-Scan drivers with Test. Jet/VTEP sensors. • Use Boundary-Scan drivers in place of In. Circuit drivers for guarding and stimulus, but retain capacitive pickup of signal. BTW 2009 4

Using Boundary-Scan for Test Stimulus What are the advantages of this ? • Test pins whose signals are not accessible • Can eliminate access (cheaper fixtures) • Validates the investment in Boundary-Scan BTW 2009 5

Using Boundary-Scan for Test Stimulus What are the advantages of this ? Boundary-Scan interface Picture from paper 11. 2 ITC 2008. BTW 2009 6

What are the challenges with active components? • Silicon devices require accurate setup information. • Connectors require very little pin information for test generation. Most of the information is external and gathered from the node data. All pins are considered either fixed or inputs. BTW 2009 7

Required Setup Information • Pin orientation: Input, Output, Bidirectional • Disabling information (DUT): All bidirectional, output and buffer pins require disabling • Disabling all devices involved in test (connected to DUT) BTW 2009 8

Incomplete Disabling Problems • Sequential logic creates variability in response • Signals may add or cancel from run to run • Causes high standard deviation. BTW 2009 9

Standard Deviation and Testability • Cpk = (Mean-LL)/(3 x Std Dev) • Cpk 1. 5 = 99. 865% Yield • Cpk 1. 0 = 93. 3% Yield BTW 2009 10

Experimental Results – Incomplete Disabling BTW 2009 11

Experimental Results Si Parts Evaluated – DDR 2 Board Coverage Potential (pins) Coverage (pins) Existing Coverage (pins) Package Type Brd 1 11* 44 0 FBGA Brd 2 32 44 0 FBGA Brd 3 41 44 0 FBGA Brd 3 38 44 0 FBGA * Coverage before resolving issues discussed on next two slides. BTW 2009 12

Experimental Results – DDR 2 FBGA BTW 2009 13

DDR 2 FBGAs are Challenging but Testable • Small part geometries and lead frame yield small signal on Vtep Sensor plate • Care must be taken to minimize on board noise sources BTW 2009 14

Si Parts Evaluated – SRAM, DRAM Board Coverage (pins) Potential Coverage (pins) Number of Package Type Devices Brd 6 - SRAM 198 252 4 100 QFP Brd 6 -DRAM 82 96 2 86 TSOP Brd 6 - DRAM 18* 96 2 86 TSOP * Coverage before resolving issues discussed on next two slides. BTW 2009 15

Experimental Results – DRAM QFP BTW 2009 16

Results of Experiments • Learnings – Noise from surrounding circuits should be minimized for best results – Disable DUT and connected devices for test stability and increased coverage – Lead frame geometry plays important role (similar to any Vtep test) BTW 2009 17

Conclusion • Active components can be tested using Boundary-Scan driven Vectorless Test Technology • Proper disabling is critical • Eliminating on board noise sources will increase coverage • Technique reduces need for access BTW 2009 18

Thank You! BTW 2009 19