Boundary Scan Sungho Kang Yonsei University Outiline l

Boundary Scan Sungho Kang Yonsei University

Outiline l l l l Introduction TAP Controller Instruction Register Test Data Registers Instructions Hardware Test Innovations PCB Test Conclusion CS&RSOC YONSEI UNIVERSITY 2

Boundary Scan l l Introduction Improve testability by reducing the requirements placed on the physical test equipment Also called § JTAG (Joint Test Action Group) Boundary Scan Standards § IEEE P 1149. 1 l Why use it? § Testing interconnections among chips § Testing each chip § Snapshot observation of normal system data l Why testing boards? § To test board is easier than to test systems l Board Test Philosophy § As a sorting process § As a repair driver § As a process monitor CS&RSOC YONSEI UNIVERSITY 3

Boundary Scan Chip Architecture l Introduction The scan paths are connected via the test bus circuitry § Connection from TDI to Sin § Connection from TDO to Sout l l The normal I/O terminals of the application logic are connected through boundary scan cells to the chips I/O pads Operation § An instruction is sent serially over the TDI line into the instruction register § The selected test circuitry is configured to respond to the instruction § The test instruction is executed and then test results can be shifted out of selected registers and transmitted over the TDO to the bus master ÄPossible to shift new data into registers using the TDI while results are shifted out and transmitted over the TDO line CS&RSOC YONSEI UNIVERSITY 4

Boundary Scan Chip Architecture CS&RSOC Introduction YONSEI UNIVERSITY 5

Board Test l Introduction Board containing 4 chips with one serial test path CS&RSOC YONSEI UNIVERSITY 6

Cost of Boundary Scan l Costs § § § l Introduction 4 or 5 pins - Test Access Port (TAP) 16 state machine - TAP controller Boundary scan register Bypass register - one stage Instruction register - 2 or more stages Impacts § § § Enhanced diagnosis Reduced test-repair looping Standardized tests Reuse of tests Reduced access problems CS&RSOC YONSEI UNIVERSITY 7

Test Access Port l l TAP Consisting of the ports associated with TMS, TCK, TDI and TDO TCK: Test Clock § Operate BS part of the ICs synchronously and independently of the built-in system clock l TDI : Test Data In § Data is shifted in at the rising edge l TDO: Test Data Out § Data is shifted out at the falling edge l TMS: Test Mode Select § TMS signals are sampled at the rising edge § Controls transitions of controller l TRST : Test Reset (Optional) § TAP's test logic is asynchronously forced into its reset mode when a logic 0 is applied to TRST CS&RSOC YONSEI UNIVERSITY 8

Test Bus l l TAP Each chip is considered to be a bus slave and the bus is assumed to be driven a bus master Ring Connection § One TMS l Star Connection § Each chip is associated with its own TMS signal l Hybrid Connection § Combined CS&RSOC YONSEI UNIVERSITY 9

Ring and Star Test Bus CS&RSOC TAP YONSEI UNIVERSITY 10

Functions of TAP Controller l l TAP Generate clock and control signals required for the correct sequence of operations Provide signals to allow loading the instructions into the Instruction Register Provide signals to shift test data into (TDI) and test result data out of (TDO) the shift registers Perform test actions such as capture, shift and test data CS&RSOC YONSEI UNIVERSITY 11

TAP Controller State Diagram l TAP Non-shaded states : auxiliary § Do not initiate a system action but are included to provide process control CS&RSOC YONSEI UNIVERSITY 12

Instruction Register l l l Instruction Register Allows instruction to be shifted into chip Can be used to specify operations to be executed and select test data registers Each instruction enables a single serial test data register path between TDI and TDO Instruction may vary per IC on the board Serial-in parallel-out register CS&RSOC YONSEI UNIVERSITY 13

Instruction Register l l Instruction Register IR must contain at least 2 shift-register-based cells which can hold instruction data These 2 mandatory cells are located nearest to the serial outputs, i. e. they are the least significant bits § Used in locating faults through the IC's l Set up CS&RSOC YONSEI UNIVERSITY 14

Test Data Registers l Test Data Register Required § Boundary Scan Register § Bypass Register l Optional § Device Identification Register : specifies manufacturer, part number, and variant § Design Specific Register : for self test, internal scan paths, etc. l l Unique Name Fixed Length CS&RSOC YONSEI UNIVERSITY 15

Bypass Register l l Bypass Register Single stage shift register When selected, the shift register is set to 0 on the rising edge of TCK with TAP controller in its Capture-DR state Provide a minimum length serial path for the test data from TDI to TDO § Test cycle is shortened § Diagnosis time is shortened CS&RSOC YONSEI UNIVERSITY 16

Boundary Scan Register l l Scan Cell Series of boundary scan cells Features § Allow testing of circuitry external to the IC § Allow testing of the core logic § Allow sampling and examination of the input and output signals without interfering the operation of the core logic § Can stay idle CS&RSOC YONSEI UNIVERSITY 17

Boundary Scan Cells l Implementation of boundary scan cell l Normal Mode Scan Cell § When Mode Test/Normal = 0, data passes from IN to OUT § Then the cell is transparent to the application logic l Scan Mode § Mode Shift/Load =1 and clock pulses are applied to Clock l Capture Mode § The data on IN can be loaded into the scan path by setting Mode Shift/Load =0 and applying one clock pulse to Clock CS&RSOC YONSEI UNIVERSITY 18

Boundary Scan Cells l Scan Cell Update Mode § Once the 1 st FF is loaded, either by a capture or scan operation, its value can be applied to OUT by setting Mode Test/Normal=1 and applying clock pulse to Update l Minimum boundary scan cell configuration for input pins § Preferrable in delay sensitive circuits CS&RSOC YONSEI UNIVERSITY 19

Instructions l Instructions Mandatory § BYPASS § SAMPLE/PRELOAD § EXTEST l Optional § § § § INTEST RUNBIST IDCODE USERCODE CLAMP HIGHZ Design specific CS&RSOC YONSEI UNIVERSITY 20

BYPASS l l Instructions Every chip must have a BYPASS register which is a test data register of length 1 Provides a single bit connection through the chip § data shifted through chip without affecting chip § shorten path to target chip l l Binary code must be all 1's If the optional device ID is not present, BYPASS instruction is forced into the latches at the parallel outputs of the Instruction Register when the TAP controller is in its Test-Logic-Reset CS&RSOC YONSEI UNIVERSITY 21

SAMPLE/PRELOAD l Instructions Used to take snapshot of normal system operation stage into the parallel instruction register § Allows the data on I/O pads of a chip to be sampled § Useful for debugging of prototypes in the development phase of a board design l Used to load values into boundary Scan cells § After power-up, the data in boundary scan registers at the output cells are not known CS&RSOC YONSEI UNIVERSITY 22

EXTEST l l Instructions Used to test circuitry external to a chip, such as the board interconnect While this instruction is executed, the core logic is isolated from the I/O pins § The test data is loaded beforehand into the boundary scan register stages using SAMPLE/PRELOAD § The loading of test vectors is concluded by bridging the TAP controller to the Update-DR state § On the falling edge of TCK the test vectors are transferred to the parallel output stage § At the receiving ends of the net, the cells at the input pins capture the test result with the controller in its Capture-DR state § The next step shifts out the test results from the input pin cells towards TDO CS&RSOC YONSEI UNIVERSITY 23

EXTEST l l Instructions Dataflow during EXTEST instruction During the time of execution of the EXTEST, only one system pin is driving a net at a time while the other connected output pins are kept at HIGHZ § This avoids boundary scan cells at the output pins being overdriven with an unknown signal value CS&RSOC YONSEI UNIVERSITY 24

INTEST l Instructions Used to apply a test vector to the application logic via the boundary scan path and to capture the response from this logic § Slow speed testing § Gives complete controllability and observability of the I/O pads of a chip l For device containing dynamic logic such as DRAM memories, refreshment of data cells may require a much higher frequency than can be obtained with this test method § Use RUNBIST CS&RSOC YONSEI UNIVERSITY 25

INTEST l Instructions Dataflow during INTEST instruction CS&RSOC YONSEI UNIVERSITY 26

RUNBIST l l Instructions Allows for the execution of a self test process The test is executed while TAP controller is in the Run. Test/Idle state § Must select the boundary scan register to be connected between TDI and TDO § All inputs to the application logic are driven by the boundary scan register during the execution of this instruction § The timing constraints have been added to ensure that the tests of all components involved are completed in one test run § When the self test is running, the boundary scan cells are used to hold the component's output to a fixed value § The signals generated in the core logic during the self test cannot enter the PCB nets § When RUNBIST is applied, the test results of all versions of a component must be the same CS&RSOC YONSEI UNIVERSITY 27

CLAMP l l l Instructions Used to control the output signals of a component to a constant level by means of a boundary scan cell In such cases the Bypass Register is connected in the TDI -TDO path on the PCB This instruction is used for instance with cluster testing, where it can be necessary to apply static guarding values to those pins of a logic circuitry which are not involved in a test The required signal values are loaded together with all test vectors, both at the start of the test and each time a new test pattern is loaded Increase the test pattern and slightly reduce the overall test rate CS&RSOC YONSEI UNIVERSITY 28

IDCODE l l Instructions If a Device Identification Register is included, the IDCODE is forced into the Instruction Register's parallel output latches while the TAP controller is in its Test-Logic-Reset state This means of accesses to the Device Identification Register permits blind interrogation of components assembled onto a PCB, making it possible to determine what components are mounted on a board CS&RSOC YONSEI UNIVERSITY 29

USERCODE l l l Instructions Must provided by the manufacturer if the Device Identification Register is included in a component and the component is user-programmable This instruction is only required if the programming can not be determined through the use of the test logic When selected, this instruction loads the userprogrammable identification code into the Device Identification Register at a rising edge of TCK and TAP controller in its Capture-DR state CS&RSOC YONSEI UNIVERSITY 30

HIGHZ l l l Instructions Force all outputs of a component to an inactive drive state Application is found in situations where a conventional incircuit test is still required The in-circuit tester may drive signals back to the component's output pins where hazards may occur if its output impedance is not high CS&RSOC YONSEI UNIVERSITY 31

Binary Counting Test Sequence l l Only two vectors are needed to detect any short Vectors for short detection § § § § l PCB Test-Algorithm V 1 V 2 Net 1 0 0 Net 2 0 1 Net 3 1 0 Net 4 1 1 The vectors V can be applied in parallel Test time is determined by log 2(n) If the test vectors are applied through a boundary scan, test time is p log 2(n) where p is the number of shift operations If the all-0 and all-1 test patterns are avoided for the short test the same test vectors can be used to detect both short and stuck-at faults § log 2(n+2) vectors are necessary and sufficient to to test a set of n nets on both type of faults CS&RSOC YONSEI UNIVERSITY 32

Binary Counting Test Sequence l PCB Test-Algorithm § Step 1 : Assign each of the n interconnect nets a successive number, starting with 1 § Step 2 : Calculate the value of log 2(n+2) in order to find the number of patterns needed § Step 3 : Assign each of driving node the calculated number of bits with a bit pattern having a binary value equal to the number assigned to the net concerned l Vectors for short detection of 6 connections § § § § Net 1 Net 2 Net 3 Net 4 CS&RSOC V 1 0 0 0 1 1 1 V 2 0 1 1 0 0 1 V 3 1 0 1 0 YONSEI UNIVERSITY 33

Walking One Sequence l PCB Test-Algorithm If there are N nets, then after N shifts of the total chain the logical 1 has walked over the all nets, one at a time § …. 0 0 0 1 § …. 0 0 1 0 l l l l The total sequence just takes N vectors It guarantees full diagnosis It works well for single fault situations and for independent co-existing of the same type Test patterns are easy to generate and test result is easily measured by a simple counter It is suited for go/no-go test but the application time is long Netlist information is needed A walking zero sequence can also be used CS&RSOC YONSEI UNIVERSITY 34

Maximal Independent Set l PCB Test-Algorithm Potential weight § depends on the bit positions of the highest and lowest bit with a value 1 in a STV l l l For a non-zero vector v=(b 0, b 1…bn…. bm) where bn=bm=1, the potential weight w is given by w=m-n+1 The vector set exhibits a very regular pattern The subsets with equal potential weight are diagonally independent CS&RSOC YONSEI UNIVERSITY 35

Aliasing Test Results l l PCB Test - Diagnositcs An aliasing test results exists when the faulty response of a set of shorted nets is the same as the fault-free response of another net In this case it cannot be determined whether or not the fault-free net is involved in the short CS&RSOC YONSEI UNIVERSITY 36

Confouding Test Results l l PCB Test - Diagnositcs It may happen that 2 or more independent shorts occur in a set of nets on a PCB A confounding test result may occur when the test results from the multiple independent faults are identical § It cannot be determined if these faults are independent l l The degree of a confounding test result is defined as the maximum number of potentially independent faults that all have the same test result A full diagnosis after a one-step test procedure is only possible if neither a confounding nor an aliasing test result exists CS&RSOC YONSEI UNIVERSITY 37

Cluster Testing l PCB Test-Cluster Testing Circuit containing boundary scan logic and non-boundary scan login § A cluster may have its inputs and outputs connected to boundary scan ICs to other circuitry or to board connectors § The test stimulus for the cluster is loaded through the TDI-TDO path into the relevant BS output cells and the responses are captured in boundary input cells and shifted out for diagnosis § Clusters may be subdivided into various types of cluster ÄMemory array of clusters ÄSingle device clusters ÄRandom logic clusters § Tester must know the PCB topology in order to select the meaningful test data out of the entire background data stream CS&RSOC YONSEI UNIVERSITY 38