BIST TestDecompressor Design using Combinational Test Spectrum Nitin
BIST / Test-Decompressor Design using Combinational Test Spectrum Nitin Yogi Vishwani D. Agrawal Auburn University, Dept. of Elec. & Comp. Eng. Auburn, AL 36849, U. S. A. 13 th IEEE / VSI VLSI Design and Test Symposium Bangalore, India July 10, 2009 13 th VLSI Design and Test Symposium 1
Outline Problem Definition p Proposed Design Method p n n p Results n n p Spectral Analysis BIST Architecture Results without reseeding Results with reseeding Conclusion July 10, 2009 13 th VLSI Design and Test Symposium 2
Problem Definition p To design a Test Pattern Generator (TPG) for Built-In Self Test (BIST) of combinational circuits achieving the following goals: n Given a set of pre-generated test vectors, replicate their effects in hardware n Low area overhead n Low test application times July 10, 2009 13 th VLSI Design and Test Symposium 3
Proposed Design Methodology Pre-generated test vectors Step 1 Spectral properties Step 2 Preprocess test vectors Determine prominent spectral components by spectral analysis July 10, 2009 BIST implementation BIST TPG gate-level netlist 13 th VLSI Design and Test Symposium 4
Walsh Functions and Hadamard Matrix w 0 Walsh functions (order 3) w 1 w 2 • Walsh functions: a complete orthogonal set of basis functions that can represent any arbitrary bitstream. • Walsh functions form the rows of a Hadamard matrix. w 3 w 4 H(3) = w 5 w 6 w 7 time July 10, 2009 13 th VLSI Design and Test Symposium 1 1 1 1 1 -1 1 1 -1 -1 1 -1 -1 1 1 1 -1 -1 1 1 -1 Example of Hadamard matrix of order 3 5
Test Vectors and Bit-streams July 10, 2009 Input 3 Input 4 Input 5 1 0 0 1 0. . 0 0 1. . 1 1 0 1. . 1 0 1 1 0 0. . 1 Input J Input 2 Vector K → 1 0 1 1 0. . 1 Outputs . . . . 13 th VLSI Design and Test Symposium . . . . 1 1 0. . 0 Time Vector 1 → Vector 2 → Vector 3 → Vector 4 → Vector 5 → Input 1 Circuit Under Test (CUT) A binary bit-stream to be spectrally analyzed 6
Spectrum: Input 1 of circuit s 5378 Theoretical random noise level (16) Spectrum of ATPG bit-stream applied to input 1 of circuit s 5378 July 10, 2009 13 th VLSI Design and Test Symposium 7
Spectrum: Input 9 of circuit s 5378 Theoretical random noise level (16) Spectrum of ATPG bit-stream applied to input 9 of circuit s 5378 July 10, 2009 13 th VLSI Design and Test Symposium 8
Effect of Noise Gate-level faults detected by 226 ATPG vectors More faults detected p Noise inserted in ATPG vectors, generated for a sample of faults (RTLthan original vectors faults), for s 5378 circuit, using increasing spectral threshold (ST) values p (i. e. , increasing noise) 226 ATPG vectors for 1602 RTL faults July 10, 2009 13 th VLSI Design and Test Symposium 9
BIST Architecture SC System clock N-bit counter with XOR gates Hadamard wave generator System clock 3 BIST clock 1 1 Spectral component synthesizer 13 th VLSI Design and Test Symposium Input 1 Input 2 Randomizer 1 Weighted pseudo-random bit-streams July 10, 2009 Proportion: SC 1 = 0. 5 SC 2 = 0. 5 1 Bit-stream To Proportion: of spectral Noise SC 1 = 0. 25 CUT SC 2 component Cellular Automata SC inserted 2 = 0. 25 BIST SC SC bit-stream 3 = 0. 5 Register with 3 Weighted random clock AND-OR gates bit-stream (W = 0. 25) Weighted pseudorandom pattern generator 2 Hadamard Components Weighted random bit-stream (W=0. 5) To CUT Input 3 10
Hadamard Wave Generator LSB CLK 3 -bit down counter; N flip-flops For H(N) Logic ‘ 1’ W 0 FF 1 W 1 FF 2 W 3 W 4 FF 3 MSB W 5 W 6 W 7 C. K. Yuen, “New Walsh-Function Generator, ” Electronics Letters, vol. 7, p. 605, 1971. July 10, 2009 13 th VLSI Design and Test Symposium 11
Generation of Weighted Random Bit-streams P 1=0. 5 P 1=0. 25 P 1=0. 5 Cellular Automata Register M Flip-flops P 1=0. 625 P 1=0. 75 P 1=0. 875 P 1=0. 9375 P 1=0. 5 Circuit No. of PI c 7552 s 15850 (comb. ) July 10, 2009 No. of Flip-flops Hadamard wave gen. (N) CA register (M) 207 6 24 600 7 28 13 th VLSI Design and Test Symposium 12
Spectral BIST Results and Area Overhead Test coverage results without reseeding (64000 vectors) Circuit Random vectors Weighted Random vectors Spectral BIST ATPG Coverage (No. of vecs) c 7552 97. 41% 97. 86% 99. 81% 100% (247) s 15850 (combinational) 96. 81% 97. 41% 98. 77% 100% (530) Area overhead comparison Spectral BIST PRPG Circuit No. of gates in circuit No. of gates % Area overhead c 7552 3513 976 27. 78 830 23. 63 s 15850 (combinational) 9772 2672 27. 34 2400 24. 56 July 10, 2009 13 th VLSI Design and Test Symposium 13
Test Coverage vs Number of Vectors July 10, 2009 13 th VLSI Design and Test Symposium 14
Test Coverage vs Number of Vectors July 10, 2009 13 th VLSI Design and Test Symposium 15
Reseeding of Spectral TPG Flip-flops Data from external tester Parallel interface Spectral BIST / Decompressor Logic To CUT Serial scan interface Mode of operation Function External Tester Mode (ETM) One-seed-per-test vector operation Hybrid BIST Mode (HBM) Used to generate test vectors and reseed flip-flops periodically July 10, 2009 13 th VLSI Design and Test Symposium 16
Spectral TPG Results with Reseeding Comparison of test data volume and test time for c 7552 No. of inputs Test data volume (bits) No. of tester cycles No. of system clock cycles Test time (us)† 247 207 51129 247 0 2 247 1 51129 0 511 ETM (parallel) 197 30 5910 197 0 2 ETM (serial) 197 1 5910 0 59 HBM (parallel) 33 30 990 33 8034 8 HBM (serial) 33 1 990 8034 18 Mode of test application No. of vecs. / seeds Conventional (parallel) Conventional (serial) Spectral BIST † assuming tester clock period Ttester=10 ns and on-chip system clock period Tclk=1 ns July 10, 2009 13 th VLSI Design and Test Symposium 17
Spectral TPG Results with Reseeding Comparison of test data volume and test time for s 15850 (combinational) No. of inputs Test data volume (bits) No. of tester cycles No. of system clock cycles Test time (us)† 530 600 318000 530 0 5 530 1 318000 0 3180 ETM (parallel) 455 35 15925 455 0 5 ETM (serial) 455 1 15925 0 159 HBM (parallel) 134 35 4690 134 20129 21 HBM (serial) 134 1 4690 20129 67 Mode of test application No. of vecs. / seeds Conventional (parallel) Conventional (serial) Spectral BIST † assuming tester clock period Ttester=10 ns and on-chip system clock period Tclk=1 ns July 10, 2009 13 th VLSI Design and Test Symposium 18
Conclusion p Proposed a TPG design methodology for combinational circuits using spectral techniques. n p Designed TPG exhibits the following: n n n p Also proposed a reshuffling algorithm to enhance spectral components. Higher test coverage than random and weighted random vectors for equal number of test vectors. Encouraging test data compression capabilities up to 95%. An order of magnitude reduction in test application time. Issues to address: n Slightly high area overhead p Overhead might reduce by: § Implementation on larger circuits § Optimum selection of spectral components by reshuffling algorithm n Increase in test time for parallel HBM p July 10, 2009 Optimum seeds and intervals for reseeding can reduce the test time. 13 th VLSI Design and Test Symposium 19
Thank you. Questions please? July 10, 2009 13 th VLSI Design and Test Symposium 20
Pre-processing of Test Vectors Reshuffling Algorithm: Input Data and Parameters: NI: No of inputs NV: No. of vectors V(1: NV, 1: NI): Test vector Set of dimensions NV x NI hd: Dimension of Hadamard matrix H: Hadamard transform matrix of dimension 2 hd x 2 hd Procedure: Vector set V appended with redundant vectors to make weighting of bit-streams of all inputs = 0. 5 for i=1 to NI Perform spectral analysis on bit-stream of input i: S = V(: , i) x H; Pick the prominent spectral component Sp(i) from S Rearrange vector set V such that maximum bits in the bit- streams of inputs 1 to i match with the picked prominent spectral components Sp(1 to i) respectively. end July 10, 2009 13 th VLSI Design and Test Symposium 21
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