Basic opamp design and compensation 12282021 1 Two

Basic opamp design and compensation 12/28/2021 1

Two stage CMOS opamp 12/28/2021 2

Two stage CMOS opamp �The third stage exist only if the load is resistive. �The first stage is typically a differential input single ended output amplifier. �The second stage is often a CS amplifier with active load. �CC is used to stabilize the amplifier. 12/28/2021 3

Two stage CMOS opamp 12/28/2021 4

Two stage CMOS opamp �The opamp gain: �The gain of the first stage a is a technology dependent parameter ( 12/28/2021 ) 5

Two stage CMOS opamp � The opamp gain: � The gain of the second stage � The gain of the third stage (note that the gain degradation due to body effect is eliminated) 12/28/2021 6

Frequency response �Typically CC causes the gain to start decreasing well below unity gain frequency. �Hence, it is reasonable to assume all capacitors can be ignored compared to CC. �For now we assume Q 16 is not present. 12/28/2021 7

Frequency response 12/28/2021 8

Frequency response � For mid-band frequencies: Assuming A 3 is 1: 12/28/2021 9

Slew rate Using PMOS transistors at the input stage can help increase SR. (why? ) 12/28/2021 10

Systematic offset voltage 12/28/2021 11

Input stage transistors � Factors affecting the type of the input transistors: � Gain � SR � Trans-conductance of the second stage drive transistors � The second pole frequency � Load resistance � Flicker noise 12/28/2021 12

Feedback amplifier � First order model of an opamp: 12/28/2021 13

Feedback amplifier � Closed loop transfer function of an amplifier: 12/28/2021 14

Settling time � Settling time: � Linear settling � Non-linear settling 12/28/2021 15

Settling time � Example: Find the minimum unity gain frequency of the opamp so that the output can settle to within 0. 1% accuracy in 0. 1 ms. 12/28/2021 16

Settling time �Solution: For C 2=10 C 1: ft=12. 3 MHz For C 2=0. 2 C 1: ft=66. 8 MHz 12/28/2021 17

Opamp compensation � We assume: � For w>>wp 1: 12/28/2021 18

Opamp compensation � The loop gain is: � And the loop gain unity gain frequency (wt)is: 12/28/2021 19

Opamp compensation � The phase margin: 12/28/2021 20

Opamp compensation � The closed loop transfer function: 12/28/2021 21

Opamp compensation 12/28/2021 22

Compensating the two stage opamp 12/28/2021 23

Compensating the two stage opamp � The first stage is assumed to be much faster and is modeled by a current source. 12/28/2021 24

Compensating the two stage opamp � If Rc=0: 12/28/2021 25

Compensating the two stage opamp � If the poles are real and widely separated, the denominator can be expressed as: 12/28/2021 26

Lead compensation � If Rc is not zero, the frequency of the zero would be: � There a number of possibilities: � Eliminating the zero: � Eliminating the second pole: � wz=1. 2 wt: 12/28/2021 27

Process and temperature independent compensation � Making Rc to change as 1/gm 7 makes the relative values of the poles and zeros frequency independent. � Hence, Veff 16/Veff 7 should be made process independent. 12/28/2021 28

Process and temperature independent compensation 12/28/2021 29

Process independent biasing 12/28/2021 30

Process independent biasing � For the special case where (W/L)15=4(W/L)13: gm 13=1/RB � Since the bias of all transistors are derived from the same network: and for p-channel transistors: 12/28/2021 31