Basic Logic Design with Verilog HDLCombinational Circuits TA

Basic Logic Design with Verilog HDL(Combinational Circuits) TA: Bo-Yuan Peng bypeng@cobra. ee. ntu. edu. tw Lecture note ver. 1 by Chen-han Tsai ver. 2 by Chih-hao Chao ver. 3 by Xin-Yu Shi ver. 4 by Bo-Yuan Peng

Outline o o o Introduction to Verilog HDL Syntax in Verilog HDL Gate-Level Modeling Test-Bench Compilation and Simulation Tools Preview of Lab Questions 2

Introduction to Verilog HDL

What is Verilog HDL? o Why using Hardware Description Language? n n n o Design abstraction: HDL ←→ layout by human Hardware modeling Reduce cost and time to design hardware Two Popular HDLs n n VHDL Verilog 4

What is Verilog HDL? o Key features of Verilog n Supports various levels of abstraction o o n Behavior level Register transfer level Gate level Switch level Simulate design functions 5

Different Levels of Abstraction o Architectural / Algorithmic Level n o Implement a design algorithm in high-level language constructs. Register Transfer Level n Describes the flow of data between registers and how a design process these data. System Algorithm Architecture Register Transfer Level Gate Level Transistor Level 6

Different Levels of Abstraction o Gate Level n o Describe the logic gates and the interconnections between them. Switch (Transistor) Level n System Algorithm Architecture Describe the transistors and Register Transfer Level the interconnections between them. Gate Level Transistor Level 7

Simplified Hardware Design Flow Verilog 8

Example: 1 -bit Multiplexer 9

Gate Level Description in 1 iv_sel in 2 n 1 sel a 1 a 2 a 1_o a 2_o o 1 out iv_sel Gate Level: you see only netlist (gates and wires) in the code. 10

Behavior Level / RTL Description always block assign RTL: you may see high level behavior in the code Behavior: event-driven behavior description construct 11

Syntax in Verilog HDL

A Simple Verilog Code module name declaration syntax in/out port/wire declaration kernel hardware gate-connection/ behavior 13

Module o o Basic building block in Verilog Module 1. 2. o o o Created by “declaration” (can’t be nested) Used by “instantiation” Interface is defined by ports May contain instances of other modules All modules run concurrently 14

Module Instantiation instance example 15

Instances o o o A module provides a template from which you can create actual objects. When a module is invoked, Verilog creates a unique object from the template. Each object has its own name, variables, parameters and I/O interface. 16

Analogy: Module vs. Class Format module m_Name( IO list ); . . . endmodule class c_Name {. . . }; Instantiation m_Name ins_name ( port connection list ); c_Name obj_name; Member ins_name. member_signal obj_name. member_data Hierachy instance. sub_instance. membe object. sub_object. member_data r_signal 17

Port Connection o Connect module port by order list n o o FA 1 fa 1(c_o, sum, a, b, c_i); Connect module port by name (Recommended) n Usage: . Port. Name (Net. Name) n FA 1 fa 2(. A(a), . B(b), . CO(c_o), . CI(c_i), . S(sum)); Not fully connected n FA 1 fa 3(c_o, , a, b, c_i); 18

Verilog Language Rule o o Case sensitive Identifiers n n n o o Digits 0123456789 Underscore _ Upper and lower case letters from the alplabet Terminate statement/declaration with semicolon “; ” Comments n n Single line: // it’s a single line comment example Multi-line: /* When the comment exeeeds single line, multi-line comment is necesssary */ 19

Data Type: Register o Register n n Keyword: reg, integer, time, real Event-driven modeling Storage element (modeling sequential circuit) Assignment in “always” block (LHS of expressions) 20

Data Type: Net o Net n n n Keyword: wire, wand, wor, triand, trior, supply 0, supply 1 Doesn’t store value, just a connection Input, output and inout ports are default “wire” 21

Four-valued Logic Value o Nets and registers in Verilog codes hold fourvalued data n n n 0 represent a logic ‘ 0’ or false condition 1 represent a logic ‘ 1’ or true condition z o o Output of an undriven tri-state driver – High-Z value Models case where nothing is setting a wire’s value 22

Four-valued Logic Value o Nets and registers in Verilog codes hold fourvalued data n x o Models when the simulator can’t (doesn’t) decide the value – un-initialized or unknown logic value n n n Initial state of registers A wire is being driven to 0 and 1 simultaneously Output of a gate with z inputs 23

Logic System o Four values: 0, 1, x/X, z/Z (not case sensitive) n n o o The logic value x denotes an unknown (ambiguous) value The logic value z denotes a high-impedance value (High-Z value) Primitives have built-in Logic Simulators describe 4 -value logic 24

Logic System: Example 0 1 X Z 0 0 0 1 X X X 0 X X X Z 0 X X X 25

Number Representation o o Format: <size>’<base_format><number> <size> - decimal specification of bits count n o Default: unsized and machine-dependent but at least 32 bits <base_format> - ' followed by arithmetic base of number n n d or D – decimal (default if no base format given) h or H – hexadecimal o or O – octal b or B – binary 26

Number Representation o o Format: <size>’<base_format><number> - value given in base of base format n n _ can be used for reading clarity x and z are automatically extended 27

Number Representation o Examples: n n n n 6’b 010_111 8’b 0110 4’bx 01 16’H 3 AB 24 5’O 36 16’Hx 8’hz gives 010111 gives 00000110 gives xx 01 gives 0000001110101011 gives 0… 0011000 gives 11110 gives xxxxxxxx gives zzzz 28

Number Representation o o o o o 659 // unsized decimal ‘h 837 ff // unsized hexadecimal ‘o 7460 // unsized octal 4 af // illegal syntax 4’b 1001 // 4 -bit binary 5’D 3 // 5 -bit decimal 3’b 01 x // 3 -bit number with unknown LSB 12’hx // 12 -bit unknown 8’d -6 // illegal syntax -8’d 6 // phrase as - (8’d 6) // underline usage 27_195_000 16’b 0001_0101_0001_1111 32’h 12 ab_f 001 // X and Z is sign-extended reg [11: 0] a; initial begin a = ‘hx; a = ‘h 3 x; a = ‘h 0 x; end // yields xxx // yields 03 x // yields 00 x 29

Net Concatenation Module B Module A Module C 3‘o 7 Representations Meanings {b[3: 0], c[2: 0]} {a, b[3: 0], w, 3’b 101} {4{w}} {b, {3{a, b}}} {b[3] , b[2] , b[1] , b[0], c[2] , c[1] , c[0]} {a, b[3] , b[2] , b[1] , b[0], w, 1’b 1, 1’b 0, 1’b 1} {w, w, w, w} 30 {b, a, b}

Operators Arithmetic Operators Relational Operators Equality Operators Logical Operators Bit-wise Operators Unary Reduction Shift Operators Conditional Operators Concatenations +, -, *, /, % <, <=, >, >= ==, !=, ===, !== !, &&, || ~, &, |, ^, ~^ &, ~&, |, ~|, ^, ~^ >>, << ? : {} 31 Excerpts from CIC training course: Verilog_9807. pdf

Operator Examples All bits are 0 logic false 32 Excerpts from CIC training course: Verilog_9807. pdf

Compiler Directives o 'define n n o 'include n n o 'define RAM_SIZE 16 Defining a name and gives a constant value to it. 'include adder. v Including the entire contents of other verilog source file. 'timescale n n 'timescale 100 ns/1 ns Setting the reference time unit and time precision of your simulation. 33

System Tasks o $monitor ($time, "%d %d %d", address, sinout, cosout); n Displays the values of the argument list whenever any of the arguments change except $time. n o $display ("%d %d %d", address, sinout, cosout); n Prints out the current values of the signals in the argument list n o $finish n n $finish Terminate the simulation 34

Gate Level Modeling

Gate Level Modeling o Steps n n n o Develop the Boolean function of output Draw the circuit with logic gates/primitives Connect gates/primitives with net (usually wire) HDL: Hardware Description Language n Figure out architecture first, then write code. 36

Primitives o o o Primitives are modules ready to be instanced Smallest modeling block for simulator Verilog build-in primitive gate n and, or, xor, nand, nor, xnor o n not, buf o o prim_name #delay inst_name( out 0, in 1, . . ); prim_name #delay inst_name( out 0, out 1, . . . , in 0); User defined primitive (UDP) n building block defined by designer 37

Case Study: Full Adder 38

Case Study: Full Adder o Co = AB + BCi + Ci. A 39

Case Study: Full Adder o sum = a b ci 40

Case Study: Full Adder o Full Adder Connection n n Instance ins_c from FA_co Instance ins_s from FA_sum 41

Test-Bench

Test Methodology o o Systematically verify the functionality of a model. Procedure of simulation n Detect syntax violations in source code Simulate behavior Monitor results 43

Test Methodology 44

Verilog Simulator 45

Testbench for Full Adder module t_full_add(); reg a, b, cin; wire sum, c_out; // for stimulus waveforms full_add M 1 (sum, c_out, a, b, cin); //DUT initial #200 $finish; initial begin #10 a = 0; b = #10 a = 1; b = endmodule 0; 1; cin cin // Stopwatch = = = = // Stimulus patterns 0; // Statements execute in sequence 0; 0; 0; 1; 1; 46

Summary o Design module / DUT n Divide-and-Conquer o n Architecture figure of each sub-module o n n o Partition the whole design into several parts Make architecture figures before you write Verilog codes Create hardware design in gate-level or RT-level Connection of sub-modules Test-bench n n n Feed input data and compare output values at right timing slots Usually describe in behavioral level Not real hardware, just like software programming (e. g. C/C++) 47

Note o Verilog is a platform n n o How to write verilog well? n n n o Support hardware design (design module) Also support C/C++ like coding (test bench) Know basic concepts and syntax Get a good reference codes (a person or some code files) Form a good coding style Hardware n n Combinational circuits (today’s topic) Sequential circuits (we won’t model them in this course) 48

Compilation and Simulation Tools Workstations X-window Verilog-XL and NC-Verilog Debussy

Workstations o Why workstations? n n o Multiple Users, multiple tasking Stable Operations How to run tasks on the workstations? n Operating System: Unix-like o o n Example: Linux Example: Solaris User Interface o o Text Mode X-Window 50

Workstations o Where are the workstations? n n http: //cad. ee. ntu. edu. tw/ You are receiving the account and the password to the workstations. o o NOTE: This account expires on 12/16/2007. Answer the lab questions before the expiration date. If you want to continue enjoying the resources on the workstations, contact the TA managing the IC design Lab to get more information. n Usually you need to attend the Special Projects held by the professors in ICS or EDA group 51

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Workstations o How can I connect to the workstations? n n n PCMan? KKMan? No! putty or pietty (Inherited from putty, dedicated to CJK environments) putty download site: o n pietty download site: o n http: //www. chiark. greenend. org. uk/~sgtatham/putty/download. html http: //ntu. csie. org/~piaip/pietty/ In the following examples, we will use pietty. 54

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IP or Domain Name Username and Password Port: 22 57

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Workstations o Basic instructions n n Change Password: passwd Log out: logout Show processes: ps (processes and PIDs) Delete a process: kill -9 PID 59

Workstations o Useful commands n n n man : manual page ls : list a folder’s contents ls –a : list all files (including the hidden files) ls –aux : list all files with detailed information cp : copy files from one folder/directory to another o n n n cp filename 1 filename 2 cp –r : copy the whole folder to another mkdir : create a folder pwd : display your current path 60

Workstations o More useful commands n n n cd : Change folder ps : display process status by process identification number and name kill -9 PID: terminate a running process o n n rm : delete files rm –r : remove the whole folder quota –v : show disk space tar : pack and compress files o o n n n kill -9 1234 -cvf : for creating compressed file -xvf : for extracting compressed file mv : move or rename file exit : turn the terminal off logout 61

X-window o Why X-window? n o Most important graphic user interface on UNIX and similar system How to use X-window? n You need an X-window server to use the Xwindow. o Not an X-window client. An X-window client is a program with GUI that runs on the workstations. 62

X-window 63

X-window o What X-window server can be used? n X-Win 32 o o n XFree 86 o o o n http: //www. starnet. com/products/xwin 32/ Student Order : US$69. 95 http: //www. xfree 86. org/ Free Need Cygwin on MS Windows Xming o o http: //www. straightrunning. com/Xming. Notes/ Free Easy to setup We will use this as an example 64

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Download and install these two 68

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X-window o o Since X-window server runs on users’ clients, we usually need our clients to have public IP. What if we are using private IP, say, wireless network for example? 72

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1. Type the DN then save 2. Select X 11 preference setup 74

3. Check “Enable X 11 forwarding 75

Run firefox (“&” means “simultaneously”) An example NOTE: DON’T DO IT OFTEN! PID 76

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Useful programs o vi n n o Powerful but not so user friendly Suitable for advanced users gedit n n n graphic user interface Analogy with notepad in Windows Suitable for beginners 78

vi 79

gedit 80

Verilog-XL and NC-verilog o Verilog-XL n n n o NC-verilog n n o Designed by Phil Moorby, the father of verilog Interpreter of verilog Designed for syntax checking and simulation Designed by Cadence Inherited from Verilog-XL In the following examples, we use NCverilog. 81

Example: Full Adder and its test-bench FA_co. v FA_sum. v module FA_co ( co, a, b, ci ); module FA_sum ( sum, a, b, ci ); input a, b, ci; output co; wire ab, bc, ca; and and or g 0( g 1( g 2( g 3( ab, bc, ca, co, a, b ); b, ci ); ci, a ); ab, bc, ca ); input a, b, ci; output sum; xor g 0( sum, a, b, ci ); endmodule 82

Example: Full Adder and its test-bench FA_gatelevel. v module FA_gatelevel ( sum, co, a, b, ci ); input a, b, ci; output sum, co; FA_co ins_c( co, a, b, ci ); FA_sum ins_s( sum, a, b, ci ); endmodule 83

Example: Full Adder and its test-bench FA_tb. v module FA_tb(); reg a, b, cin; wire sum, c_out; FA_gatelevel fa 1 ( sum, c_out, a, b, cin ); initial #200 finish; initial begin #10 #10 end a a a a = = = = 0; 0; 1; 1; b b b b = = = = 0; 1; cin cin = = = = 0; 0; 1; 1; endmodule 84

Example: Full Adder and its test-bench 85

Example: Full Adder and its test-bench o How to observe the designed circuit? n o debussy How to observe the timing diagram? n n n $fsdb. Dumpfile("filename"); $fsdb. Dumpvars; n. Wave (part of debussy) 86

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Select the files then Add 91

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Double-click all of the signals you want to observe 100

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Preview of Lab Questions

Preview of Lab Questions o o The lab questions themselves will be released on 11/29. Here some clues and some necessary preprocessing for the lab questions are revealed. 104

Preview of Lab Questions o Clue 1 n In the previous example for the full adder, we didn’t count the propagation delay on. What if we suffer from gate delays? How to simulate the delays? o o Hint: Check the usage of the primitives of the gates AGAIN. Clue 2 n Study Unit 11 and Unit 12 in the textbook very hard. The lab questions will involve the content in it. o Hint: You are encouraged to try to construct and simulate the circuits in unit 11 and unit 12. 105

Preview of Lab Questions o Pre-process n Review problem 7 in our midterm examination. What is the answer? Try to design the circuit using verilog in gate level. 106

Information for the PC Room Hour o Timeslots n n n o Place n o o 11/20 9: 00 ~ 12: 00 11/20 14: 00 ~ 17: 00 11/27 9: 00 ~ 12: 00 PC Classroom, EEII 132 Regarded as office hours Encouraged to choose any of the slots to come 107