Axilog Language Support for Approximate Hardware Design Amir

Axilog: Language Support for Approximate Hardware Design Amir Yazdanbakhsh Jongse Park Divya Mahajan Bradley Thwaites Anandhavel Nagendrakumar Sindhuja Sethuraman Kartik Ramkrishnan Nishanthi Ravindran Rudra Jariwala Abbas Rahimi Hadi Esmaeilzadeh Kia Bazargan Georgia Institute of Technology University of Minnesota UC San Diego Georgia Institute of Technology Alternative Computing Technologies (ACT) Lab DATE 2015

Approximate computing Embracing error • Relax the abstraction of near-perfect accuracy in general-purpose computing/communication/storage • Allow errors to happen during computation/communication/storage – Improve resource utilization efficiency • Energy, bandwidth, capacity, … – Improve performance • Build acceptable systems from intentionally-made unreliable software and hardware components • Avoid overkill and worst-case design 2

Avoiding Worst-Case Design Approximate Computing Generality Efficiency Performance Application Cost Precision Reliability Determinism Cost Programming Language Compiler Architecutre Microarchitecture Circuit Physical Device 3

Goals Design the first HDL for 1) Approximate Hw Design 2) Approximate Hw Reuse 3) Approximate Synthesis Criteria Approximate HDL shall be 1) High-level 2) Automated 3) Backward compatible 4

Safety in Hardware Approximate Precise Datapath Controller Clock 5

Axilog Annotations Design Annotations relax (relax_local) restrict (restrict_global) Reuse Annotations approximate critical bridge 6

Design Annotations 7

Relaxing Accuracy Requirements module ripple_carry_adder(a, b, c_in, c_out, s) … full_adder f 0(a[0], b[0], c_in, w 0, s[0]) full_adder f 1(a[1], b[1], w 0, c_out, s[1]) relax (s); … 8

Relaxing Accuracy Requirements module ripple_carry_adder(a, b, c_in, c_out, s) … full_adder f 0(a[0], b[0], c_in, w 0, s[0]) full_adder f 1(a[1], b[1], w 0, c_out, s[1]) relax (s); … 9

Scoping Approximation (relax_local) module full_adder (a, b, c_in, c_out, s) … relax_local (s); … … full_adder f 0 (…) full_adder f 1(…) relax (s[0]); … 10

Scoping Approximation (relax_local) module full_adder (a, b, c_in, c_out, s) … relax_local (s); … … full_adder f 0 (…) full_adder f 1(…) relax (s[0]); … 11

Restricting Approximation 12

Restricting Approximation 13

Restricting Approximation 14

Restricting Approximation Globally module full_adder(a, b, c_in, c_out, s); … approximate output s; relax (s); … endmodule … restrict_global(s[31: 0]); 15

Restricting Approximation Globally module full_adder(a, b, c_in, c_out, s); … approximate output s; relax (s); … endmodule … restrict_global(s[31: 0]); 16

Reuse Annotations 17

Outputs Carrying Approximate Semantics 18

Critical Inputs … critical input reset; critical input clock; … reset State Register Next State Logic Output Logic clock 19

Bridging Approximate Wires to Critical Inputs … and a 1(s, a 0, a 1); relax (s); bridge (s); multiplexer m 0(s, a 0, a 1, out); … 20

Bridging Approximate Wires to Critical Inputs … and a 1(s, a 0, a 1); relax (s); bridge (s); multiplexer m 0(s, a 0, a 1, out); … 21

Baseline Synthesis Flow Highest frequency with minimum power and area 22

Relaxability Inference Analysis Circuit under analysis with Axilog annotations Identify the wires which are driving unannotated wires or annotated with restrict within the module under analysis Identify the relaxed outputs of the instantiated submodules Marks any wire that affects a globally restricted wire as precise Safe to approximate gates 23

Approximate Synthesis Flow Axilog Code Axilog Compiler Safe to Approximate Gates 24

Measurements Tools for Synthesis and Energy Analysis • Synopsys Design Compiler • Synopsys Primetime Timing Simulation with SDF back annotations • Cadence NC-Verilog Standard Cell Library • TSMC 45 -nm multi-Vt • Slowest PVT corner (SS, 0. 81 V, 0 C) for baseline results 25

Benchmarks Arithmetic Computation, Signal Processing, Robotics, Machine Learning, Image Processing Sobel # lines: 143 # Annotations Kogge-Stone # lines: 353 # Annotations Wallace Tree # lines: 13, 928 # Annotations Neural Network # lines: 21, 053 # Annotations Image Processing Arithmetic Computation Machine Learning Design: 6 Reuse: 3 Design: 1 Reuse: 1 Design: 5 Reuse: 3 Design: 4 Reuse: 3 FIR # lines: 113 # Annotations Brent-Kung # lines: 352 # Annotations K-means # lines: 10, 985 # Annotations Forward. K # lines: 18, 282 # Annotations Inverse. K # lines: 22, 407 # Annotations Signal Processing Arithmetic Computation Machine Learning Robotics Design: 6 Reuse: 5 Design: 1 Reuse: 1 Design: 7 Reuse: 3 Design: 5 Reuse: 4 Design: 8 Reuse: 4 26

Tr n m ea be l So G eo ee eu ra l N ce al la ne Error ≤ 5% W to -S gg e Ko ea ns m 1. 9 K- 2. 0 In ve rs e. K d. K ar rw Fo R FI un g en t-K Br Energy Reduction Error ≤ 10% 1. 8 1. 7 1. 6 1. 5 1. 4 1. 3 1. 2 1. 1 1. 0 27

n m ea be l So G eo ee Tr eu ra l N ce al la ne Error ≤ 5% W to -S gg e Ko ea ns m K- 2. 6 In ve rs e. K d. K ar rw Fo R FI un g en t-K Br Area Reduction Error ≤ 10% 2. 4 2. 2 2. 0 1. 8 1. 6 1. 4 1. 2 1. 0 28

Output Quality Degradation in Sobel 0% Quality Loss 5% Quality Loss 10% Quality loss is nearly indiscernible to the eye Yet provides 57% energy savings 29

Energy Reduction for Different PVT Corners 100% (SS, 0. 81 V, 125°C) (SS, 0. 81 V, 0°C) 90% 70% 60% 50% 40% 30% 20% 10% ea n G eo m be l al eu r So ce la al N ee Tr on St W K og g e- -m K e s ea n K In ve r se d. K ar w FI R Fo r re nt -K un g 0% B Energy Reduction 80% 30

Axilog Energy Savings 54% First HDL for Approximation • Design • Reuse • Automation • High-level • Backward-compatibility Area Code Reduction Annotations 1. 9× 2 -12 http: //www. act-lab. org/artifacts/axilog 31