Automating ThermoMechanical Warpage Estimation of PCBsPCAs Using a

Automating Thermo-Mechanical Warpage Estimation of PCBs/PCAs Using a Design-Analysis Integration Framework Presenter: Russell Peak Authors: Manas Bajaj (Georgia Tech), Russell Peak (Georgia Tech), Dirk Zwemer (Akro. Metrix), Thomas Thurman (Rockwell Collins), Lothar Klein (LKSoft), Giedrius Liutkus (LKSoft), Kevin Brady (NIST), John Messina (NIST), Mike Dickerson (Inter. CAX) v 3 - 2006 -07 -07

http: //eislab. gatech. edu/pubs/conferences/2006 -user 2 user-bajaj/ Abstract Accurate prediction, validation and reduction of thermally-induced PCB warpage are critical for enhancing manufacturing yield and reliability in time-to-market driven electronics product realization. In this paper, we describe a methodology to simulate thermally-induced warpage of PCBs and PCAs. We will demonstrate this analysis methodology using the following path: read ECAD designs from Mentor Graphics Board Station, identify features relevant to warpage analysis, create idealized analysis models, select solution technique and create solver-specific models (e. g. ANSYS and ABAQUS models for finite-element solution), identify warpage hotspots and calculate metrics to assist PCB/A designers in reducing warpage. We shall also present initial results from experimental verification of this technique using a shadow moiré (Ther. Moiré®) method. This methodology provides highly automated simulation capabilities using analysis concepts, idealizations, and solution techniques for modularized and configurable simulation studies. It leverages open standards including ISO 10303 (STEP AP 210 – www. ap 210. org and Standard Data Access Interface - see www. jsdai. net). Resources: (a) http: //www. Inter. CAX. com/warpage (b) http: //eislab. gatech. edu/projects/nist-warpage/ 2 MB, RP et al. , PWB/PWA Warpage, May 2006

Contents n Warpage Context Definition and impact — PCB/A features affecting warpage — Requirements for warpage analysis — n Sample simulation results and validation Bare boards (PCBs) — Assembled boards & chip pkgs. (PCAs, BGAs) — n Methodology and tools Multi-representation architecture — Tool availability — n Summary 3 MB, RP et al. , PWB/PWA Warpage, May 2006

Doc/Proc/Reg Guidelines Layout Functional Part Symbol & Footprint Placement Design Requirements Electronics Product Realization Routing Learn today Utilize tomorrow Review Corrections Release Environmental Build Fabricate 4 MB, RP et al. , PWB/PWA Warpage, May 2006 Assemble Test/Inspect

Warpage - Definition n WARPAGE is out of plane deformation of the artifact, caused by differential (non-homogenous) shrinkage or expansion of elements composing the artifact. Out of plane deformation of a linear element Warpage of 2 D artifacts ( basic modes) Saddle Deformation Basic Model = ( b L 2 T) / t where L: Undeformed Length; t: Undeformed Thickness; T: Temperature Change; b: Specific Coefficient of Thermal Bending 5 MB, RP et al. , PWB/PWA Warpage, May 2006 Bowl Deformation

PCA/B Warpage - Illustration Undeformed Shape Deformed Shape 6 MB, RP et al. , PWB/PWA Warpage, May 2006

Warpage – Impact and Requirements Ref: Thinking Globally, Measuring Locally Editorial by Patrick Hassell, Akro. Metrix Impact n Low manufacturing yield and high rework of interconnects Lack of co-planarity of component footprints — Fine pitch technology — Low solder paste volume — Requirements n Managing warpage requirements Enforce local warpage requirements — Relax global warpage requirements — 7 MB, RP et al. , PWB/PWA Warpage, May 2006

Warpage Effects [after Ding, 2003; Zwemer, 2006; et al. ] Estimated Impact: $100 M / year Factors — — — — Consequences CTE mismatch: global & local Temperature / humidity variation Temperature / humidity gradient Material rigidity Thermal conductivity Geometric size & aspect ratio Component layout Underfill Molding 8 MB, RP et al. , PWB/PWA Warpage, May 2006 Vias Solder Balls PWB — — — Misregistration Solder opens Solder shorts Delamination Solder fatigue Die cracking Die/Chip BGA Substrate

Contents n Warpage Context Definition and impact — PCB/A features affecting warpage — Requirements for warpage analysis — n Sample simulation results and validation Bare boards (PCBs) — Assembled boards & chip pkgs. (PCAs, BGAs) — n Methodology and tools Multi-representation architecture — Tool availability — n Summary 9 MB, RP et al. , PWB/PWA Warpage, May 2006

Complex Features Affecting Thermo-Mechanical Behavior PCB Layout PCB Level Features on PCB - Notional Figure Footprint occurrence Via Traces Complete trace curve not shown Stackup Land PCB outline M 150 P 2 P 11184 M 150 P 1 P 21184 10 MB, RP et al. , PWB/PWA Warpage, May 2006 Plated through hole Mechanical (tooling / drilling) hole

Complex Features Affecting Thermo-Mechanical Behavior PCA Level: Complex Components Isometric View Side View Mold Resin Si Chip Die Attach Solder Resist Cu Foil BT-Resin Core Cu Foil Solder Resist Solder Balls (Diagonal Grid Pattern) Photo: www. shinko. co. jp 11 MB, RP et al. , PWB/PWA Warpage, May 2006

Contents n Warpage Context Definition and impact — PCB/A features affecting warpage — Requirements for warpage analysis — n Sample simulation results and validation Bare boards (PCBs) — Assembled boards & chip pkgs. (PCAs, BGAs) — n Methodology and tools Multi-representation architecture — Tool availability — n Summary 12 MB, RP et al. , PWB/PWA Warpage, May 2006

Requirements for Warpage Analysis n n n Availability of a rich product model — ECAD design details — PCB layer stackup details — Material behavior and properties Analysis model creation capabilities — Idealized PCB/A features — Boundary conditions — Thermal loading FEA model creation and solution capabilities — FE mesher — FE solver 13 MB, RP et al. , PWB/PWA Warpage, May 2006

Rich Product Model http: //eislab. gatech. edu/pubs/journals/2004 -jcise-peak/ Traditional Tools Electrical CAD Tools Mechanical CAD Tools Systems Engineering Tools Eagle Pro/E Doors Mentor Graphics AP 210 … Teamcenter Requirements NX AP 203, AP 214 AP 233, Sys. ML Collective Product Model Standards-based Submodels AP 210 Gap-Filling Tools Xai. Tools PWA-B AP 2 xx pgef PWB Stackup Tool, Engineering … Framework Tool 14 MB, RP et al. , PWB/PWA Warpage, May 2006 Building Blocks: • Information models & meta-models: • International standards • Industry specs • Corporate standards • Local customizations • Modeling technologies: • Express, XML, UML, OWL, … EPM, LKSoft, … Theorem, … STEP-Book AP 210, SDAI-Edit, . . . Instance Browser/Editor

STEP AP 210 (ISO 10303 -210) Domain: Electronics Design R ~1200 standardized concepts (many applicable to other domains) Development investment: O(100 man-years) over 10+ years Configuration Controlled Design of Electronic Assemblies, their Interconnection and Packaging Interconnect Assembly Printed Circuit Assemblies (PCAs/PWAs) Product Enclosure Die/Chip Packaged Part Printed Circuit Substrate (PCBs/PWBs) Die/Chip 15 MB, RP et al. , -PWB/PWA Warpage, May 2006 2003 -04 Adapted from 2002 -04 version by Tom Thurman, Rockwell-Collins Package External Interfaces

STEP AP 210 (ISO 10303 -210) http: //www. ap 210. org Used for warpage analysis Scope Functional Models Requirements Models • Functional Unit • Interface Declaration • Network Listing • Simulation Models • Signals • Test Bench • • Rules Models • Design • Manufacturing • … Assembly Models • • • User View Design View Component Placement Material Product Complex Assemblies with Multiple Interconnects Design Control • Geometric Dimensioning and Tolerancing 16 MB, RP et al. , PWB/PWA Warpage, May 2006 Design Constraints Interface Allocation Component / Part Models • Analysis Support • Package • Material Product • Properties • “White Box”/ “Black Box” • Test Bench • • • Configuration Mgmt Identification Authority Effectivity Control Net Change • • Interconnect Models Usage View & Design View Bare Board Design Layout Templates Layers and Layer Technologies Stackup Geometric Models 2 D 3 D CSG, Brep… EDIF, IPC, GDSII compatible “trace” model

Example Design in STEP Book AP 210 Pro (PCB Layout View) Originating ECAD Model from: Mentor Board Station Current Tool: STEP Book AP 210 v 2. 3 Current Model based on: STEP AP 210 17 MB, RP et al. , PWB/PWA Warpage, May 2006

Example Design in Xai. Tools PWA-B 2. 0. b 1 Stackup Editor Originating ECAD from: Mentor Board Station Current Tool: Xai. Tools PWA-B v 2. 0. b 1 Current Model based on: STEP AP 210 18 MB, RP et al. , PWB/PWA Warpage, May 2006

PCB Warpage Analysis Model Creation Context Single Layer View Building Block-based Analysis Model length width AP 210 -based Manufacturing Product Model … Top view of “effective” grid elements in top layer of the PCB Effective Material Property Computation … thickness Side view of the PCB with “effective” grid elements across the stratums Given: Context Attributes Grid (Sieve) • Thermal loading profile Size • Boundary Conditions (mostly displacement) • Idealize PWB stackup as a layered shell 19 MB, RP et al. , PWB/PWA Warpage, May 2006 • Thermal loading profile • Boundary Conditions (mostly displacement) • Idealize PWB stackup as a layered shell

Contents n Warpage Context Definition and impact — PCB/A features affecting warpage — Requirements for warpage analysis — n Sample simulation results and validation Bare boards (PCBs) — Assembled boards & chip pkgs. (PCAs, BGAs) — n Methodology and tools Multi-representation architecture — Tool availability — n Summary 20 MB, RP et al. , PWB/PWA Warpage, May 2006

Chopped PCB Regions for Analysis in Xai. Tools PWA-B 2. 0. b 1 First (Top) Design Layer Second (Bottom) Design Layer 21 MB, RP et al. , PWB/PWA Warpage, May 2006

Example Design - Coeff. of Thermal Bending Results in Xai. Tools PWA-B 2. 0 Regions with greatest mismatch 22 MB, RP et al. , PWB/PWA Warpage, May 2006

Example Design – Finite Element Model Creation and Solution Input to ANSYS APDL-based description for creating and solving the finite-element model Xai. Tools PWA-B 2. 0. b 1 23 MB, RP et al. , PWB/PWA Warpage, May 2006

Example Design – FEA Warpage Results Out-of-plane deformation Conditions T = 125 deg. C - uniform heating from 25 deg. C to 150 deg. C Y-min and Y-max edges are fully constrained 24 MB, RP et al. , PWB/PWA Warpage, May 2006

Overall Process - Circuit Board Stackup Design & Warpage Analysis Using AP 210 (WIP) GIT and NIST EEEL in collaboration with Akro. Metrix, Inter. CAX/LKSoft, and Rockwell Collins width length … ECAD and STEP AP 210 -based Product Model Design Improvement Feedback Analysis Building Block Model (idealized bodies with effective material properties) PCB Warpage Profile (given: thermal profile + boundary conditions) CTB Map (smeared property to identify material distribution) http: //eislab. gatech. edu/projects/ 25 MB, RP et al. , PWB/PWA Warpage, May 2006 thickness Identification of warpage “hotspots” on a PCB

PCB Warpage: Validation Results http: //eislab. gatech. edu/pubs/conferences/2004 -eurosime-zwemer/ Simulation Results Physical Measurements in Ther. Moiré oven chamber www. Akro. Metrix. com Measurement Results SMM - FEA Mesh Model 0 C 26 MB, RP et al. , PWB/PWA Warpage, May 2006

Board. Station “Module 10” Example in SB 210 Pro v 2. 3 9 layer board 27 MB, RP et al. , PWB/PWA Warpage, May 2006

Module 10: Idealization Grids for Effective Material Properties 28 MB, RP et al. , PWB/PWA Warpage, May 2006

Module 10: CTB Maps 29 MB, RP et al. , PWB/PWA Warpage, May 2006

Module 10: FEA Warpage Results out-of-plane deformation (Uz) in inches delta T = 150 C 30 MB, RP et al. , PWB/PWA Warpage, May 2006

Recent Production Test Cases —- Need more Mentor designs for testing — (collaboration opportunity!) 31 MB, RP et al. , PWB/PWA Warpage, May 2006

PCA viewed in STEP Book AP 210 Pro Design-07 ry d a t e ete i r op Del r P e ag m I Co-efficient of Thermal Bending (per deg C) 32 MB, RP et al. , PWB/PWA Warpage, May 2006 559 components 10 circuit layers Source ECAD Tool: Zuken Visula Warpage Profile (z-axis deflection) – 25 C to 150 C

PCA viewed in STEP Book AP 210 Pro Design – 02 MOD ry d a t e ete i r op Del r P e ag m I Co-efficient of Thermal Bending (per deg C) 33 MB, RP et al. , PWB/PWA Warpage, May 2006 1757 components 12 circuit layers Source ECAD Tool: Zuken Visula Warpage Profile (z-axis deflection) – 25 C to 150 C

Contents n Warpage Context Definition and impact — PCB/A features affecting warpage — Requirements for warpage analysis — n Sample simulation results and validation Bare boards (PCBs) — Assembled boards & chip pkgs. (PCAs, BGAs) — n Methodology and tools Multi-representation architecture — Tool availability — n Summary 34 MB, RP et al. , PWB/PWA Warpage, May 2006

PCA Warpage Automated Analysis Model Creation 35 MB, RP et al. , PWB/PWA Warpage, May 2006 PCB = printed circuit board (bare board) PCA = printed circuit assembly = PCB + components, etc.

Case 1: 1 PBGA 265 on top Automated PCA design warpage analysis U 3 36 MB, RP et al. , PWB/PWA Warpage, May 2006

Case 2: 2 PBGA 265 s on top U 3 37 MB, RP et al. , PWB/PWA Warpage, May 2006

Case 3: 3 PBGA 265 s on top Qualitative comparison - Different board & components (somewhat similar) - Good warpage shape results comparison - Similar total warpage results (2. 2 mils vs. 1. 7 mils = ~23% delta) [Ding, 2004] results Inter. CAX results Xai. Tools Electronics (SBIR Phase 1 prototype) 38 MB, RP et al. , PWB/PWA Warpage, May 2006 Total Warpage for T=150 C: = 0. 0022 in [scaled from 0. 07 mm @ T=183 C] Total Warpage for T=150 C: 0. 0017 in

Case 4: PCA with top & bottom PBGAs Analytical model in IDA-STEP as imported from AP 203 Produced by idealizing AP 210 -based PCB design (from ECAD tool) and combining with idealized chip package models in Xai. Tools Electronics prototype (XE), and exporting as AP 203 Bare PCB Two PBGA 265 (top side) One PBGA 441 (bottom side) 39 MB, RP et al. , PWB/PWA Warpage, May 2006 Dense off-pitch body interactions (challenging for FEA meshers)

Case 4: PCA with top & bottom PBGAs Mesh model in Abaqus as imported from native Abaqus format 40 MB, RP et al. , PWB/PWA Warpage, May 2006 [xx - view needs update]

Case 4: PCA with top & bottom PBGAs FEA mesh model in Abaqus (cont. ) Mesh in dense chip package solder ball regions Auto-generated mesh between chip package substrate layers, solder balls, and PCB layers [xx - view needs update] (same region in full wireframe view) 41 MB, RP et al. , PWB/PWA Warpage, May 2006

Case 4: PCA with top & bottom PBGAs Solved FEA model in Abaqus PCA top Warpage (u 3 = out-of-plane deformation) Preliminary Warpage Results (to be further validated in Phase 2) Results - Case 4: - Demonstrated FEA meshing feasibility (main challenge) - Good results, trends, and compatibility with similar cases [Ding, 2004; Powell, 2006] - Results reveal anticipated asymmetric effects - High fidelity PCB model considers local feature density differences - Future work will try more effective idealizations (ex. shells) & correlate with physical measurements PCA bottom 42 MB, RP et al. , PWB/PWA Warpage, May 2006 Bare board (PCB) warpage

Case 5: PBGA Chip Package on Sample PCB Deformation magnitude results: PCA 6230 (w/ PBGA 441) Known Results [Zeng, 2004; Shinko] XCP + Patran pre-processing Abaqus solving and Patran post-processing Inter. CAX SBIR Phase 1 Results XE + Simmetrix pre-processing Abaqus solving and post-processing Phase 1 Results - Case 5 - Excellent comparison of deformation pattern - Very good comparison of max. warpage values (1. 61 mils vs. 1. 50 mils = ~7% delta) - Possible deviation causes: different meshing approach, different solver version, etc. 43 MB, RP et al. , PWB/PWA Warpage, May 2006

PCA Warpage Capabilities NIST SBIR FY 05 Program Inter. CAX Phase 1 Project July, 2005 -January, 2006 http: //www. Inter. CAX. com/warpage/ n Main Phase 1 results — — — n Successfully demonstrated feasibility of auto-generating complex FEA models from AP 210 -based ECAD designs Included localized board properties key for warpage prediction Achieved good correlation with published results (within 7%) Reduced simulation time by 80% for benchmark case Automatically simulated design configurations ~5 times larger than previously practical Excellent outlook for next steps — — Phase 2 Services and tools for industry 44 MB, RP et al. , PWB/PWA Warpage, May 2006

Contents n Warpage Context Definition and impact — PCB/A features affecting warpage — Requirements for warpage analysis — n Sample simulation results and validation Bare boards (PCBs) — Assembled boards & chip pkgs. (PCAs, BGAs) — n Methodology and tools Multi-representation architecture — Tool availability — n Summary 45 MB, RP et al. , PWB/PWA Warpage, May 2006

Multi-Representation Architecture (MRA) for Design Analysis Integration Tree View Bare PWB Electrical Mechanical Warpage Manufacturing Product Model Manufacturability Analysis Product Model PTH Fatigue Context-Based Analysis Model Layered Shell Effective Materials Properties Analysis Building Blocks Finite Element Solution Method Model 46 MB, RP et al. , PWB/PWA Warpage, May 2006

Multi-Representation Architecture (MRA) for Design Analysis Integration Stepping-Stone Model View ECAD Tools and Manufacturable Product Model (STEP AP 210 -based) Analyzable Product Model Context-Based Analysis Model APM Analysis Building Block Printed Wiring Assembly (PWA) Solution Method Model CBAM APM Component Solder Joint SMM FABB Component Solder Joint Printed Wiring Board (PWB) ABB PWB T 0 ABBYSMM body 1 body 4 body 3 body 2 Solution Tools (ANSYS, ABAQUS …) 47 MB, RP et al. , PWB/PWA Warpage, May 2006

MRA-based Model Browser Design Artifacts – PCA, PCB, Components, etc. Design Libraries Product-specific Analysis Models Reusable Analysis Models Solution Models and Results – Finite Element Model, etc. 48 MB, RP et al. , PWB/PWA Warpage, May 2006

Tool Availability n STEP Book AP 210 Pro v 2. 3 — — n Xai. Tools PWA-B v 2. 0 — — n Imports & views Mentor Graphics designs: Board. Station (Expedition under development) Enables enrichment & AP 210 output Stackup editor Bare board warpage analysis Xai. Tools Electronics v 1. 0 (prototype) — Assembled board warpage analysis Product & Service Information: http: //www. Inter. CAX. com/warpage/ 49 MB, RP et al. , PWB/PWA Warpage, May 2006

Collaboration Opportunities n Test cases n Georgia Tech research project 50 MB, RP et al. , PWB/PWA Warpage, May 2006

Contents n Warpage Context Definition and impact — PCB/A features affecting warpage — Requirements for warpage analysis — n Sample simulation results and validation Bare boards (PCBs) — Assembled boards & chip pkgs. (PCAs, BGAs) — n Methodology and tools Multi-representation architecture — Tool availability — n Summary 51 MB, RP et al. , PWB/PWA Warpage, May 2006

Summary n Automated board warpage analysis — — n Bare board stackup design and warpage analysis Assembled board warpage analysis Use of rich product models to drive high-fidelity analyses — AP 210 interface to Mentor Graphics ECAD tools n Commercial tools and services n Collaboration opportunities — — Georgia Tech research project Test cases 52 MB, RP et al. , PWB/PWA Warpage, May 2006

References n Inter. CAX warpage resources — n Georgia Tech-NIST project for bare board warpage simulation — n n n http: //www. Inter. CAX. com/warpage/ http: //eislab. gatech. edu/projects/nist-warpage/ Hai Ding (2004) Prediction and Validation of Thermomechanical Reliability in Electronic Packaging. Doctoral Dissertation, Georgia Institute of Technology, Atlanta. Reinhard Powell (2006) Development of FE Prediction Tools and Convective Solder Reflow Projection Moiré Warpage Measurement System. Doctoral Dissertation, Georgia Institute of Technology, Atlanta. Sai Zeng (2004) Knowledge-based FEA Modeling for Highly Coupled Variable Topology Multi-body Problems. Doctoral Dissertation, Georgia Institute of Technology, Atlanta. 53 MB, RP et al. , PWB/PWA Warpage, May 2006

NIST Disclaimer This document may identify commercial product names and materials by other parties to describe certain procedures or to provide concrete examples (i. e. , to help clarify abstract concepts via specific instances). In no case does product or material identification imply recommendation or endorsement by the authors or their organizations, nor does it imply that such items are necessarily the best available for the purpose. Company, product, or service names may be included that are trademarks or service marks of others. 54 MB, RP et al. , PWB/PWA Warpage, May 2006

55 MB, RP et al. , PWB/PWA Warpage, May 2006