ATCA LLP CARRIER BLOCK DIAGRAMS LAST UPDATE 09052007

ATCA LLP CARRIER BLOCK DIAGRAMS LAST UPDATE 09/05/2007

Master / Slave Structure SLOT A (n) MASTER/SLAVE CARD_PRESENT TCLK_PRESENT DATAPATH TRIGGER CLOCK SYNCs And DATA MANAGERS CLOCK AND SYNCS SWITCHES SLOT B (n+1) MASTER/SLAVE CARD_PRESENT TCLK_PRESENT DATAPATH TRIGGER CLOCK SYNCs And DATA MANAGERS CLOCK AND SYNCS TCLK

200 Mhz Clock and Clock SYNC distribution MASTER GTS 200 MHz $07 – D 0 GTS_CLOCK SWITCH $07 – D 1 CLOCK_ SYNC FANOUT VIRTEX 4 LX 25 DATA DISTRIBUTON CORE SWITCH $07 – D 2 PLL SEGMENT CLOCK_ SYNC 100 MHz PPC_CLOCK SMB INSP SEGMENT SWITCH $08 – D 1 VIRTEX 4 FX 100 PPC_CLOCK MAIN FPGA MGT CLOCK SYSTEM 100 MHz 200 MHz SLAVE SEGMENT 200 MHz $07 – D 0 GTS_CLOCK SWITCH $07 – D 1 CLOCK_ SYNC FANOUT VIRTEX 4 LX 25 DATA DISTRIBUTON SEGMENT SWITCH $07 – D 2 PLL SEGMENT SWITCH $08 – D 1 100 MHz SMB INSP SEGMENT CLOCK_ SYNC PPC_CLOCK VIRTEX 4 FX 100 MGT CLOCK SYSTEM 100 MHz 200 MHz MAIN FPGA PPC_CLOCK TCLK

100 MHz clock with missed periods as SYNC event GTS ADCs CLOCK SYNC distribution SYNC_AUX MASTER SYNC_RTN GTS_SYNC CORE SEGMENT FANOUT SWITCH SEGMENT SYNC_AUX SYNC_RTN SLAVE GTS_SYNC SEGMENT FANOUT SWITCH SEGMENT TCLK

Serializers SYNC signal distribution 10 MHz clock signal (the patterns must be equal at any rising edge) MASTER GTS TRIGGER FPGA CORE SEGMENT FANOUT SWITCH MAIN FPGA SEGMENT SLAVE SEGMENT TRIGGER FPGA SEGMENT FANOUT SWITCH MAIN FPGA TCLK

Bcast & Msg Handler Serialized B_cast_str 0 B_cast_str 1 GTS Status (7 downto 0) SERIALIZERS 8 1 GTS MEZZANINE B_cast_data (7 downto 0) FROM REMOTE (TCLK) x 6 8 LX 25 FANOUT TO MAIN FPGA, LOCALS MEZZANINES, AND REMOTE MEZZANINES (TCLK) 8 8 MAIN FPGA LLP Status (7 downto 0) Msg_data (7 downto 0) Msg_str 0 Msg_str 1 8 LLP Status (7 downto 0) Msg_data (7 downto 0) Msg_str 0 Msg_str 1 LX 25 8 8 FROM REMOTE (TCLK) Concentrator SEG/CORE MEZZANINE x 4 TO REMOTE (TCLK)

TRIGGER Handler serialized FROM REMOTE (TCLK) Trig_val (1 downto 0) 8 GTS MEZZANINE Trig_Rej (1 downto 0) FANOUT TO OTHERS DEST 8 Lt_data (7 downto 0) Lt_Strobe 8 LX 25 Tv_data (7 downto 0) Tv_Strobe Local_Trigger (1 downto 0) Trig_req (1 downto 0) CORE MEZZANINE Trig_req (1 downto 0) x 4 TCLK MAIN FPGA

TRIGGER & BCAST Handler (parallel) 44 lines Trig_req (1 downto 0) Alignement BUS (3 lines) Trig_req (1 downto 0) 10 pairs (20 lines) Trig_val (1 downto 0) Lt_data (7 downto 0) Sync Lt_Strobe Tv_data (7 downto 0) Tv_Strobe B_cast_data (7 downto 0) B_cast_str 0 8 8 8 TCLK Sync_rtn SERs / DESERs 8/ DESERs 1 8 1 4 lines GTS MEZZANINEs Trig_Rej (1 downto 0) B_cast_str 1 8 GTS Status (7 downto 0) 8 8 200 lines 44 lines CMC #1 CMC #2 CMC #3 44 lines CMC #4 44 lines FX 100 266 / 448 ~50% of LX 25_FF 668

Using 1 16 bit port : 128 words/event 256 bytes/event 6 channels 1536 bytes 16 bit bus @ 100 MHz Need 7. 68µs (20µs avaible @ 50 KHz) 1536*4 = 6144 byte/Event 16 bit bus @ 200 MHz Need 15. 36µs (20µs avaible @ 50 KHz 8 pairs ; 16 I/O Data_A (15 downto 0) 18 bit Empty_A Data_Ready_A Data_Request_A Data_A (15 downto 0) Empty_A Serializer 18 bit 1 Mx 18 DPRAM Deserializer 20 bit Data_Ready_A Data_Request_A Max 325 Events stored 6. 5 msec@50 KHz X 4 Mezzanines Data Rate Required 307. 2 Mb/sec @50 KHz Peak Bandwidth [Mb/sec] Peak Event Rate [KHz] Fast Ethernet [100 Mbit/sec] 11 1. 8 1 G Ethernet [1. 25 Gbit/sec] 94 15. 3 PCI Express [2. 5 Gbit/sec] 225 36. 6 Data Readout Protocol Data readout engine

MGT Clocking Layout MUX (***) User SFP could be used as 1 GEnet or PCIExpress DAQ without FABRIC 200 MHz GTS Clock ATCA FABRIC CH 12 ATCA FABRIC CH 11 MUX MGTclk M 34/N 34 Rocket. IO A B 101 Rocket. IO A B 102 ATCA FABRIC CH 10 MGTclk AP 28/AP 29 PHASE LOCKED MUX ATCA FABRIC CH 09 Rocket. IO A B 103 ATCA FABRIC CH 08 MUX ATCA FABRIC CH 07 100 MHz GTS Clock Rocket. IO A B 105 ATCA FABRIC CH 06 MUX ATCA FABRIC CH 05 LOCAL 100 MHz Rocket. IO A B 106 ATCA FABRIC CH 04 MUX ATCA FABRIC CH 03 MGTclk J 1/K 1 MUX 100 250 MHz PCI Express JITTER ATTENUATOR ATCA FABRIC CH 02 ATCA FABRIC CH 01 Rocket. IO A B 110 MUX MGTclk AP 3/AP 4 Rocket. IO A B 109 Rocket. IO A B 112 MUX OPTICAL SFP Rocket. IO A B 113 MUX PCI Express SFP Rocket. IO A B 114 ATCA FABRIC CH 15 ATCA FABRIC CHxx ATCA FABRIC CH 13 ATCA FABRIC CH 14

ATCA Zone 1 IPMI Address FPGA 0 Temp MAX 1617 A Address $18 IPMI A IPMI B FPGA 1 Temp MAX 1617 A Address $19 FPGA 2 Temp MAX 1617 A Address $4 C MAIN FPGA (FX 100) FPGA 1 Sw LX 25 Address $60 Fast Ethernet FPGA 2 Trigger LX 25 Address $61 I 2 C Multiplexer SFP Clock Temp Sens MAX 6626 Address $48 Temp Sens MAX 6626 Address $49 Temp Sens MAX 6626 Address $4 A SFP Lanes Temp Sens MAX 6626 Address $4 B CMC 1 Address $50 I 2 C bus layout CMC 2 Address $51 CMC 3 Address $52 DC-DC ATC 210 Address ? CMC 4 Address $53 Mon. ADC MAX 1239 Address ? IO Expander ? Address ? 1 K EEPROM ? Address ?

ATCA Zone 1 IPMI Address IPMI A MANUAL SW IPMI B MAIN FPGA (FX 100) RMT JTAG Connector (Front Panel) Fast Ethernet JTAG SWITCH CONF[1. . 0] SEL PROGRAM [1. . 0] TCK I 2 C Multiplexer TMS TDI TDO INIT X 7 (4 Mezzanines + 3 FPGAs) Slow control layout (JTAG Management)

TCLK Port Layout

-48 V DC ATCA Power Supply (maximum) ATC 210 (210 W) M 48/P 12 DC DC Fusing P 3 V 3_BOOT M 48 V-3. 9 A 188 W HS ENABLE 10 x LTM 4600 55 W LINEAR REGULATORS DC to DC Converter P 3 V 3 -5 A 16. 5 W MEZZANINE 1 P 3 V 3/P 2 V 5 -1. 5 A VCCAUX Fpga 1 Linear Reg DC to DC Converter P 3 V 3 -5 A 16. 5 W MEZZANINE 2 P 5 V 0/P 2 V 5 -1. 5 A VCCAUX Fpga 2 Linear Reg DC to DC Converter P 3 V 3 -5 A 16. 5 W MEZZANINE 3 P 5 V 0/P 2 V 5 -0. 05 A VCCAUX MGT Linear Reg DC to DC Converter P 3 V 3 -5 A 16. 5 W MEZZANINE 4 P 5 V 0/P 1 V 8 -0. 5 A PROMS Linear Reg P 5 V 0/P 1 V 5 -2. 6 A VTTTXs Linear Reg P 12 V-14. 2 A 171 W P 12/P 5 V 0 DC DC P 3 V 3 -7 A 23 W P 12/P 3 V 3 DC DC P 3 V 3 -7 A 23 W P 12/P 2 V 5 DC DC P 2 V 5 -7 A 17. 5 W MAIN BOARD P 12/P 1 V 2 DC DC P 1 V 2 -9 A 11 W FPGAs CORE P 12/P 1 V 2 DC DC P 1 V 2 -5 A 6 W FPGA MGT P 12/P 1 V 8 DC DC P 1 V 8 -5 A 9 W MGT BUFFERS P 5 V 0/P 1 V 5 -0. 2 A VTTRXs Linear Reg MAIN BOARD DC-DC Efficency is estimated at least 90%

Case 1 : PCIExpress 1 Mx 36 DPRAM PCIExpress 1 Mx 36 DPRAM PCIExpress 1 Mx 36 DPRAM ADCs PCIExpress PRE PROCESSING PCIExpress 1 Mx 36 DPRAM 1 Mx 36 DPRAM PCIExpress 1 Mx 36 DPRAM PCIExpress

Case 2 : 1 G Ethernet switch 1 Mx 36 DPRAM GEthernet Switch EB FARM 1 Mx 36 DPRAM 1 Mx 36 DPRAM 1 Mx 36 DPRAM

Case 3 : PCIExpress (full mesh) PCIExpress 1 Mx 36 DPRAM PCIExpress 1 Mx 36 DPRAM PCIExpress 1 Mx 36 DPRAM PCIExpress 1 Mx 36 DPRAM 1 Mx 36 DPRAM PCIExpress 1 Mx 36 DPRAM PCIExpress