# Asynchronous logical networks II Digital Systems M 1

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Asynchronous logical networks II Digital Systems M 1

State variable coding impact on the behaviour ? X 1 Y 1 X 2 Y 2 Safe again…. With the last coding. . 00 01 11 10 A 00 11 00 00 00 Z 0 (Transition table NOT a Karnaugh map) B 11 11 10 00 00 0 The transition indicated by the red arrow is very dangerous. Theoretically from 10 (stable for input 01) with input 11 the state should switch to 01 (stable – dashed red arrow). But one of the two state variables necessarily switches before the other C 10 00 10 01 00 0 D 01 00 00 01 00 1 X 1 Y 1 X 2 Y 2 00 00 01 11 10 11 00 00 00 0 11 11 10 00 00 0 10 01 00 00 01 00 1 In the case of the green arrow (10 ->00) Y 1 is the first to change and the system reaches the state 00 (wrong !) which is stable with input 11 ! In the case of the blue arrow (10 ->11) where Y 2 switches first the system reaches the state 11 which for 11 input shows a further race (once again a double state change from 11 to 00). If in this case Y 2 switches first the system reaches the wanted state 01 (stable) with input 11 otherwise the system goes back to state 10 with a possible oscillation. Everything depends on the combinatorial network delays A race is a state transition where two ore more state variables must switch concurrently A race is critical if a wrong stable state is reached because of non concurrent state variables change 2

Another (non primitive) state table N. B. this isn’t the safe Combined inputs-states effects X 2 X 1 Y 2 Y 1 00 01 11 10 A 00 D A C B 0 0 B 01 B A A B 0 0 C 10 A C C C 1 0 D 11 D A Z 1 Karnaugh blue -> transition Green -> race Red -> stable state X 2 X 1 Y 2 Y 1 00 01 11 10 Z A 00 11 00 10 01 0 B 01 01 00 00 01 0 D 11 11 00 1 C 10 00 10 10 10 0 This table (among other problems) has a critical race. A is stable with input 01. If the input should switch to 10 (double input change) the state to be reached should be B (black solid arrow). In practice there are two possibilities: either X 1 switches first or the other way round. If X 2 switches first the input transition indicated by the red arrow (00 ->10) occurs leading to to stable state C with 10 ! If X 1 switches first the blue transition occurs which in turn can lead to different situations if starting from state A-00 (with input 00 and theoretical destination D-11) either Y 1 or Y 2 switches first. In the first case it is possible that the wanted final state is reached (violet dashed transition). In the second case (dashed green transition) the system reaches C stable again! It must be noticed that further input or states delays could provoke even different dynamic transitions!! In this table we have supposed a double input change which must in any case be avoided 3

How to cope with this situation ? Setting aside the input problems let’s analyse all the races (green) of the state variables that is all transitions which imply the change of two state variables. The previous table can be modified. Multiple transitions. In circled orange the modifications X 2 X 1 Multiple Transition Y 2 Y 1 00 01 11 10 Z A 00 11 00 10 01 10 0 B 01 01 00 00 01 0 D 11 11 01 00 11 00 01 1 C 10 00 10 11 0 Transition change In the first column from C the system should switch to A and then to D. It is therefore possible to switch directly to D. By so doing a multiple transition from A(00) to D(11) (A->C->D) is possible. Future state change Some remarks: • Multiple transitions are not always possible (more are the stables states in a column more unlikely are multiple transitions) • In the columns where only a stable state is present it is not necessary to insert multiple transitions provided no oscillations can occur • Multiple transitions induce network delays 4

Let’s consider the safe initial synthesis X 1 y 1 X 2 y 2 00 01 11 10 Z 00 01 00 00 00 0 01 01 11 00 00 0 11 00 11 10 00 0 Here we have a race. Theoretically since there is only one stable state in the column no problems should arise but if the variables switching times are different an oscillation is always possible. Better a multiple transition (11 ->00) 10 00 00 1 Z = Y 1 !Y 2 Y 1 = y 1 t+t = (!x 1 x 2 y 2 + x 1 x 2 y 1) t Y 2 = y 2 t+t = (!x 1!x 2!y 1 + !x 1 x 2 y 2) t 5

Analysis of this asynchronous sequential circuit (inputs X 1, X 2 , Reset and output Z) • Detect the state variables and their equations and using the algebra theorems simplify them indicating what theorems have been used • Detect the state transition table and its problems (if any) • Detect all possible malfunctions and provide a table solving them • Synthesize the initial transition table (after removing the possible races) using SR feedback 6

Y 1 Y 2 Leaving aside Reset Y 1= !(!x 1 !x 2) (y 1 + x 1 y 2) = (x 1+x 2)(y 1+ x 1 y 2)= x 1 y 1 + x 1 y 2 + x 2 y 1 + x 1 x 2 y 2= = x 1 y 1 + x 1 y 2 + x 2 y 1 Idempotence ! Y 2 = !(!x 2 y 1 + !(x 1 x 2 + y 2)) = !(!x 2 y 1) (x 1 x 2+y 2)= (x 2 +!y 1) (x 1 x 2+y 2)= = x 1 x 2 + x 1 x 2!y 1 + x 2 y 2 + !y 1 y 2= x 1 x 2 + x 2 y 2 + !y 1 y 2 Z = y 1!y 2 7

A gate system is controlled by two pushbuttons X 1 and X 2. When closed the gate will be opened only after the sequence 10 -00 -01 is activated. Once open the gate will remain open until the closure sequence 11 -01 -11 is activated. Once closed the gate will remain closed and will be opened only when another open sequence is activated. Design the system with the Mealy model and a primitive state diagram. Once derived the state variables expressions implement the system in VHDL and by simulation check the correctness of your design inserting the correct and the wrong sequences. Use process and «if» structures in VHDL. X 1 X 2, Z 00, 0 A 00, 0 10, 0 01, 0 H B 11, 0 G 00, 0 10, 0 C 01, - 11, - D 00, 1 11, 0 F 01, 1 E 01, 0 11, 0 00, 1 01, 1 00, 0 10, 0 01, 1 VHDL Bidirectional_lock 11, 1 00, 1 01, 1 00, 1 11, 1 L 10, 1 M 10, 1

Y 1= x 1 y 1 + x 1 y 2 + x 2 y 1 Y 2 = x 1 x 2 + x 2 y 2 + !y 1 y 2 Z = y 1!y 2 X 1 y 1 X 2 y 2 00 01 11 10 00 01 00 0 01 01 01 11 11 00 11 11 10 00 10 11 10 1 01 is never stable and reacheable (it can be reached only from 00 with 11 input BUT is unstable) 9

X 1 y 1 X 2 y 2 00 01 11 10 00 01 00 0 01 01 01 11 11 00 11 11 10 0 In red the only critical race 10 00 10 11 10 1 X 1 y 1 X 2 y 2 00 01 11 10 00 01 00 0 01 01 01 11 11 0 Table without critical races 11 10 11 11 10 00 10 11 10

X 1 y 1 X 2 y 2 00 01 11 10 00 01 00 0 01 - - 11 - 0 11 11 10 0 Simplified equivalent table (how must it be modified to insert a don’t care in the only transition using state 01 ? ) 10 00 10 11 10 1 Y 1 = y 2 + X 2 y 1 + X 1 y 1 Removed race Y 2 = X 2 y 2 + X 1 X 2 X 1 y 1 X 2 y 2 00 01 11 10 00 01 00 0 01 01 01 11 11 0 11 11 10 00 10 11 10 1 Initial table without critical race (zeros red/blue -> R=1 S=0 with black zeros , ones red/blue -> S=1, R=0 with black ones) S 1 = X 1 y 2 R 1 = !X 1!X 2!y 2 S 2 = X 1 X 2 R 2 = !X 2 y 1 11

Incompletely specified state/transition tables X 1 y 1 X 2 y 2 00 01 11 10 Z 00 00 01 00 10 0 01 00 01 11 11 0 The green transitions can NEVER occur since two simultaneous inputs changes can never occur …. . 11 00 01 11 10 00 00 11 10 1 X 1 y 1 X 2 y 2 00 01 11 10 00 00 01 -- 10 0 01 00 01 11 -- Z 0 01 11 10 00 -- 11 10 1 … and therefore can be substituted with ”don’t care” Y 1=X 1 Y 2=X 2 The network is combinatorial as it could be immediately detected (the stable states coincide with the inputs !!!). A table where each state is stable for only one input configuration is a primitive table 12

How is an asynchronous sequential network designed? - 1 1 st step: a primitive state diagram must be designed. If for each transition a new state is reached (or inserted) no problem, provided the history of the circuit is correctly interpreted otherwise the state number explodes. It must be understood the time development of the circuit and to detect the states which correct represent this develooment. There are no algorithms to design the state diagram but the human brain only Safe again X 1 X 2, Z 00, 0 01, 0 11, 1 • • Mealy (but could be Moore) The transitions outputs are don’t cares since their values are not important (the difference is only WHEN the change occurs) • 01, - • Primitive table From C with input 01 the transition is not to B otherwise the output would be activated without the correct sequence (see circuit history) 01 A 01, 0 00, 0 11, - B 10, - 00, 0 10, 0 01, 0 11, 0 D 10, 0 C 10, 0 F 11, 0 E 01, 0 • The states D, E and F do not belong to the correct sequence 13

How is an asynchronous sequential network designed? - 2 2 nd step: primitive state table (the transition which would imply the change of two inputs variables are don’t cares) X 1 X 2, Z 00, 0 A 01, 0 00, 0 11, 1 11, - B X 1 C 10, 0 01, - 10, 0 01, 0 11, 0 D 10, 0 F 11, 0 E X 2 00 01 11 10 A A, 0 B, 0 -, - D, 0 B A, 0 B, 0 C, - -, - C -, - E, - C, 1 D, - D A, 0 -, - F, 0 D, 0 E A, 0 E, 0 F, 0 -, - F -, - E, 0 F, 0 D, 0 01, 0 14

How is an asynchronous sequential network designed? - 3 3 rd step: compatible states detection for the state reduction. Two states are compatibile if, where specified, for the same inputs they provide the same outputs (where specified) and switch to the same states or to compatible states. Implication triangular table. Two by two comparison between states. If the outputs (where defined) are different for the same input configuration the states are incompatible. Otherwise in the square the condition (if any) uder which they could be compatible is recorded. A and B X 1 uncoditionally X 2 compatible 00 01 11 10 A and C compatible if B and E compatible B A A, 0 B, 0 -, - D, 0 B A, 0 B, 0 C, - -, - C C -, - E, - C, 1 D, - D D A, 0 -, - F, 0 D, 0 E A, 0 E, 0 F, 0 -, - E, 0 F, 0 D, 0 F -, - C and D incompatible becuase of the outputs -BE BE -- CF E BE CF -- F BE BE CF -- -- D E A B C Two states are compatible if the implications are cyclic or if there are no conditions (as is the case for DE , AB etc). The compatibility IS NOT transitive Two by two compatible states (introducing step by step the couples) ([AB], [AD]) ([AB], [AD], C, [DE]) ([AB], [AD], C, [DE], [DF]) ([AB], [AD], C, [DE], [DF], [EF]) A state can be added to a state set if compatible with all belonging states (and so on) Maximal compatibility classes ([AB], [AD], C, [DEF). NB A state can belong to more classes 15

Compatibility classes: states set two for two compatible Maximal compatibility class: a class to which no states can be added “Coverture” condition: each state of the initial table must be present in a least one final class “Closure” condition: the future states of a class for each input , if not indifferent, must belong to the same compatibility class The set of all naximal compatibility class is always closed and e covered The minimum states set doesn’t consist necessarily of maximal classes If not all maximal classes or non-maximal classes are chosen coverture and closure must be carefully checked NB In case of fully specified tables (without don’t cares) the coverture consists of all maximal classes (disjoint !) which obviously satisfy the closure condition too (indistinguishable states) X 1 X 2 00 01 11 10 A A, 0 B, 0 -, - D, 0 B A, 0 B, 0 C, - -, - C -, - E, - C, 1 D, - D A, 0 -, - F, 0 D, 0 E A, 0 E, 0 F, 0 -, - F -, - E, 0 F, 0 D, 0 [A, B] [C] [D, E, F] => => => a b g These are three maximal compatibility classes (not all the compatibility classes !!) which satisfy the closure and the coverture (the maximal class [AD] hasn’t been used) 16

How is an asynchronous sequential network designed? - 4 4° step: coding X 1 NB In this coding there is a problem; races ! X 2 00 01 11 10 X 1 y 1 X 2 y 2 -, - a a, 0 b, - g, 0 a 00 C, 1 D, - b -, - g, - b, 1 g, - -, - F, 0 D, 0 g a, 0 g, 0 A, 0 E, 0 F, 0 -, - E, 0 F, 0 D, 0 A A, 0 B, 0 -, - D, 0 B A, 0 B, 0 C, - C -, - E, - D A, 0 E F X 1 00, 0 01, - 11, 0 b 01 -, - 11, - 01, 1 g 11 00, 0 11, 0 -, - 10 [A, B] => a (right sequence) [C] => b (safe opened) [D, E, F] => g (out of the right sequence) If in a table there are no multiple transitions which solve the races, the only possible solution is to increase the number of states (which allow multiple transitions removing the races) 00 01 11 10 X 1 y 1 X 2 y 2 11, - -, - 00 01 11 10 00 00, 0 01, - 10, 0 01 -, - 11, - 01, 1 11, - 11 10, 0 11, 0 10 00, 0 - -, - 11, 017

How is an asynchronous sequential network designed ? - 5 X 1 y 1 X 2 y 2 00 01 11 10 00 00, 0 01, - 10, 0 01 -, - 11, - 01, 1 11, - 11 10, 0 11, 0 10 00, 0 -, - 11, 0 - X 1 y 1 X 2 y 2 00 01 11 10 00 00, 0 01, - 10, 0 01 -, - 11, - 01, 1 11, - 11 10, 0 11, 0 10 00, 0 -, - 11, 0 Direct feedback Y 2 = X 2 y 2 + X 1 X 2 + X 1 y 1 + X 1 y 2 Z = !y 1 y 2 Y 1= !X 1 y 2 + y 1 y 2 + X 1!X 2 Why these networks differ from the previous ones ? 1) Mealy And with SR feedback? ? ? 2) States minimizationn 3) Different coding 18

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Using all maximal compatibility classes - 6 X 1 X 2 00 01 11 10 A A, 0 B, 0 -, - D, 0 Couples of compatible states B A, 0 B, 0 C, - -, - ([AB], [AD], C, [DE], [DF], [EF]) C -, - E, - C, 1 D, - D A, 0 -, - F, 0 D, 0 E A, 0 E, 0 F, 0 -, - F -, - E, 0 F, 0 D, 0 [A, B] [C] [D, E, F] [AD] a b g d => => All maximal classes What about A and D found in two maximal compatibility classes? What choice? It is indifferent, possibly avoiding the races !!! X 1 Multiple choices X 2 X 1 X 2 00 01 11 10 a a/d, 0 a, 0 b, - g/d, 0 a, 0 b, - g, 0 a 00 10, 0 01, - 11, 0 b -, - g, - b, 1 g/d, - b -, - g, - b, 1 g, - b 01 -, - 11, - 01, 1 11, - g a/d, 0 g, 0 g/d, 0 g, 0 g 11 11, 0 d a/d, 0 a, 0 g/d, 0 d d, 0 a, 0 g, 0 d 10 10, 0 00, 0 11, 0 00 01 11 10 X 2 00 01 11 10 10, 0 20

Using all maximal compatibility classes - 7 X 1 y 1 X 2 y 2 00 01 11 10 01, 0 a 00 10, 0 01, - 11, 0 b 01 -, - 11, - 01, 1 11, 0 g 11 11, 0 10, 0 d 10 10, 0 00, 0 11, 0 This table has two columns with only one stable state (inputs 00 and 10) and therefore no critical races. It is however always better to avoid the double state variables change. Therefore in a with input 10 we insert 01 as future state. If we want to avoid output glitches during the transition we can insert a 0 Y 2 = X 1 + X 2 y 2 Y 1 = !X 1!X 2 + !X 1 y 2 + X 1 y 1 + !X 2 y 2 Z = !y 1 y 2 With SR ? ? 21

Previous example Multiple transitions (races in green) X 2 X 1 Y 3 Y 2 Y 1 00 01 11 10 Z A 00 11 00 10 01 0 B 01 01 00 00 01 0 D 11 11 00 1 C 10 00 10 10 10 0 X 2 X 1 11 10 Z 010 001 0 A 000 Y 3 Y 2 Y 1 00 01 11 10 100 010 001 0 A 000 011 000 100 B 001 001 000 000 001 0 D 011 111 000 1 D 011 111 011 1 C 010 000 010 010 010 0 ? 000 ? E 100 110 000 --- 000 - --- - This is a Karnaugh map E 100 ? 110 F 101 ? ? ? F 101 --- G 111 ? 011 ? 110 ? G 111 011 110 --- 110 - H 110 ? 111 ? 100 ? H 110 111 100 --- 100 - --- Right ? 22

A previous exercise again An asynchronous sequential network has two inputs X 1 and X 2 and an output Z. The inputs X 1 and X 2 never change at the same time. The output Z modifies its value only when a rising edge of X 1 or of X 2 occurs: in the first case Z=1, in the latter Z=0 X 1 X 2 00 A A 01 E 11 - 10 B H - C B 1 C - E C D 0 D A - C D 0 B C BD D BD ----- E ----- CF CF G CF ----- H ----- GE GE A B X 1 X 2 00 C D E F a b g d AE BH CD FG 01 11 10 G E A E F - 0 F - G F B 1 a a a d b 0 G H G F - 1 b b a g b 1 H H E - B 1 g a a g g 0 d b d d b 1 23

Resulting network X 1 X 2 00 01 11 10 a a a d b 0 b b a g b 1 g a a g g 0 d b d d b 1 Please notice that the table is not primitive: this because we reach a through different paths X 1, X 2 00, 01 10 10, 00 a, 0 01 b, 1 00, 01 10, 00 11 11 d, 1 g, 0 01, 11 11, 10 Two stable states per column; races risks !!! 24

First coding (with races) X 1 X 2 00 y 1 y 2 01 11 10 0 a 00 00 00 10 11 0 b 1 g 01 00 00 01 01 0 g g 0 b 11 11 00 00 00 01 11 1 d b 1 d 10 11 01 10 10 11 01 1 X 2 00 01 11 10 a a a d b b b a g g a a d b d Critical race (green) Z = y 1 Y 2 = X 1 y 2 + X 1!X 2 + !X 2 y 1 Y 1 = !X 2 y 1 + X 1!y 2 + y 1!y 2 25

Races elimination X 1 X 2 00 01 11 10 a a a d b b b a g g a a d b d X 1 X 2 00 y 1 y 2 01 11 10 0 a 00 00 00 10 11 b 1 g 01 00 00 01 01 g g 0 Error !! 10 stable !! b 11 11 00 00 00 01 11 d b 1 d 10 11 01 10 10 11 01 Z = y 1 Y 1 = y 1 y 2 + !X 2 y 1 + X 1 y 2 + X 1!X 2 Y 2 = !X 2 y 1 + y 1!y 2 + X 1!y 2 X 1 X 2 00 y 1 y 2 01 11 10 a 00 00 00 10 11 10 0 g 01 00 00 01 01 0 b 11 11 00 00 01 11 1 d 10 11 01 10 10 11 01 1 26

Another solution First redundant coding X 1 X 2 00 a b 01 11 10 a d b 0 a g b 1 g a a g g 0 d b d d b 1 11 10 a 000 000 010 001 0 b 001 000 011 001 1 g ? ? 01 011 000 111 001 011 0 d 010 001 010 000 0 e 100 000 -- -- -- - z 101 100 -- -- -- - h 111 101 -- -- -- - q 110 -- -- - 27

Second redundant coding a X 1 X 2 00 01 11 10 a a d b 0 a g b 1 b b g d a b a d g b Adjacency diagram a 000 b 001 101 X 2 00 01 11 10 a 000 000 010 001 0 b 001 000 101 100 001 1 011 001 -- -- -- 001 -- - d 010 011 001 1 g 100 000 100 0 101 -- -- 100 -- -- - 111 -- -- - 110 -- -- - y 3 y 2 y 1 011 d 010 g 100 28

Second redundant coding X 1 X 2 y 2 y 1 00 01 11 10 a 00 000 010 001 0 b 01 000 101 100 001 1 11 001 -- -- -- 001 -- - d 10 001 011 001 010 001 011 001 1 y 2 y 1 00 01 11 10 0 0 1 - 1 1 0 - 100 - y 3 Z = y 1 + y 2 y 3 = 0 g 00 000 100 0 01 -- -- 100 -- -- - Y 3 = X 1 X 2 y 1 + X 1 y 3 Y 1 = X 1!X 2!y 3 + X 1 y 1!y 3 + !X 2 y 1 + !X 2 y 2 Y 2 = y 2!y 1 + X 1 X 2!y 1!y 3 11 --- -- - 10 -- -- - y 3 = 1 29

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Exercise A Moore asynchronous sequential network has two inputs X ( «Input» ) and CK ( «Clock» ) and an output Z ( «Output» ). Both X and CK are initially 0. a) Upon the first positive edge of CK (0 to 1) following the condition X=1 the output becomes 1 and so remains until the successive positive transition of CK when the output becomes in any case 0 b) The output remans 0 until a positive edge sampling X=0. After this event back to point a) NB: In the following solution the time distance beween two consecutive positive edges of CK is called «period» 31

NB. After generating a 1 between two consecutive positive edges of CK, a period with output=0 is must elapse and CK MUST sample a X=0 input before the output can become 1 again X, CK 00 A, 0 01 00 01 B, 0 11 01 10 10 00 X, 0 Y, 1 11 01 X=0 sampled Restart C, 0 01 11 Z, 1 00 10 Ready for activating the output=1 11 10 11 W, 1 10 00 B J, 1 00 11 Here the output is 1 for a CK period Careful! Before a new output=1 is possible one period with output=0 must be inserted and X=0 must be sampled ! A zero was 01 sampled M, 0 11 Here output=0 since a period with output=1 period is elapsed 10 11 01 N, 0 00 00 10 R, 0 00 Q, 0 01 M, N, R, Q -> X=1 sampled again. A period with X=0 sampled must in any case elapse A Moore asynchronous sequential network has two inputs X ( «Input» ) and CK ( «Clock» ) and an output Z ( «Output» ). Both X and CK are initially 0. a) Upon the first positive edge of CK (0 to 1) following the condition X=1 the output becomes 1 and so keeps until the successive positive transition of CK when the output becomes in any case 0 32 b) The output keeps 0 until a positive edge sampling X=0. After this event back to point a)

X, CK 00 01 11 10 A A B - X 0 B A B C - 0 C - B C X 0 B ----C -----X ----- CY CY X A - Y X 0 Y - Z Y W 1 Z ----- Z J Z Y - 1 W YM YM W J - M W 1 J ZB J J B - W 1 M - Q M N 0 N R - M N 0 R R B - N 0 Q R Q M - 0 Y YM XN AR YM AR XN XN BQ AR AR CM CM YM BQ XN N AR XN M R Q ZB ----- A BQ CM AR CM B BQ XN XN CM C X ---BQ ----- BQ Y Z W J M N R 33

X, CK 00 01 11 10 A A B - X 0 B A B C - 0 C - B C X 0 B ----C -----X ----- CY CY X A - Y X 0 Y - Z Y W 1 Z ----- Z J Z Y - 1 W YM YM W J - M W 1 J ZB J J B - W 1 M - Q M N 0 N R - M N 0 R R B - N 0 Q R Q M - 0 Y YM XN AR YM AR XN XN BQ AR AR CM CM YM BQ XN N AR XN M R Q ZB ----- A BQ CM AR CM B BQ XN XN CM C X ---BQ ----- BQ Y Z W J M N R [ABC] [AX] [YZ] [JW] [MNQ] [NR] [a] [b] [g] [d] [e] [z] Maximal compatibility classes 34

[ABC] [AX] [YZ] [JW] [MNQ] [NR] [a] [b] [g] [d] [e] [z] X, CK 00 01 11 10 A A B - X 0 B A B C - 0 C - B C X 0 X A - Y X 0 Z Y W 1 Z Y - 1 - M Y Z W J J J W 1 J B - - Q M N 0 N R - M N 0 R R B - N 0 Q R Q M - 0 M With all maximal classes X, CK 00 01 11 10 a a, b a a b 0 b a, b a g b 0 g d g g d 1 d d a e d 1 e z e e e, z 0 z z a e e, z 0 35

[ABC] [AX] [YZ] [JW] [MNQ] [NR] [a] [b] [g] [d] [e] [z] X, CK 00 01 11 10 a a b 0 ABC a 000 01 11 10 000 001 0 b 001 000 011 001 0 a a, b b a, b a g b 0 X g d g g d 1 YZ g 011 010 1 d d a e d 1 JW d 010 000 110 010 1 e z e e e, z 0 MNQ e 110 111 110 110 0 z z a e e, z 0 NR z 111 000 110 0 In red the chosen states Race 36

Y 2 Y 1 Y 0 X, CK 00 01 11 10 a 000 000 001 0 b 001 000 000 011 001 0 g 011 010 011 011 010 1 d 010 010 000 110 010 1 e 110 111 110 110 110 0 z 111 000 110 0 111 101 110 0 101 - 100 - - 0 100 - 000 - - 0 Multiple transition 37

Y 2, Z X, CK 00 Y 2 Y 1 Y 0 01 11 10 000 000 001 000 000 011 001 0 011 010 011 011 010 010 000 110 010 1 110 111 110 110 0 100 - 000 - - 0 111 101 110 0 101 - 100 - - 0 111 101 110 0 100 - 000 - - 0 111 110 110 0 Z = !Y 2 Y 1 Y 2 = y 2 y 1 + y 2 y 0 + XCKy 1!y 0 38

Y 1 X, CK 00 Y 2 Y 1 Y 0 01 11 10 Y 2 Y 1 Y 0 X, CK 00 01 11 10 000 000 001 000 000 011 001 0 011 011 010 1 010 010 000 110 010 1 110 110 110 0 100 - 000 - - 0 111 101 110 0 101 - 100 - - 0 111 101 110 0 100 - 000 - - 0 111 110 110 0 Y 1 = Xy 1 + !y 2 y 1 y 0 + y 2 y 1!y 0 + !CKy 1 + XCK!y 2 y 0 39

Y 0 X, CK 00 Y 2 Y 1 Y 0 01 11 10 X, CK 00 Y 2 Y 1 Y 0 000 01 11 10 000 001 0 000 000 001 000 011 001 0 011 011 010 1 010 010 000 110 010 1 110 110 110 0 100 - 000 - - 0 111 101 110 0 101 - 100 - - 0 111 101 110 0 100 - 000 - - 0 111 110 110 0 Y 0 = X!y 1 y 0 + !X!CKy 2 + X!CK!y 1 + CK!y 2 y 1 y 0 + !Xy 2 y 1 y 0 40

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[ABC] [AX] [YZ] [JW] [MNQ] [NR] [a] [b] [g] [d] [e] [z] X, CK 00 01 11 10 A A B - X 0 B A B C - 0 C - B C X 0 X A - Y X 0 X, CK 00 01 11 10 Y - Z Y W 1 a a b 0 a 000 Z J Z Y - 1 b a -- g b 0 W J - M W 1 g d g g d J J B - W 1 d d a e M - Q M N 0 e z e N R - M N 0 z z a R R B - N 0 Q R Q M - 0 Non maximal classes [ABC] [X] [YZ] [JW] [MNQ] [R] [a] [b] [g] [d] [e] [z] Covered and closed set X, CK 00 01 11 10 000 001 0 b 001 000 --- 011 001 0 1 g 011 010 1 d 010 000 110 010 1 e z 0 e 110 111 110 110 0 e z 0 z 111 101 --- 111 0 101 - 100 - - 0 100 - 000 - - 0 42

Y 2, Z Max X, CK 00 Y 2 Y 1 Y 0 01 11 10 X, CK 00 Y 2 Y 1 Y 0 000 000 001 000 011 001 0 011 011 010 010 000 110 010 1 100 - 000 - - 0 101 - 100 - - 0 111 101 110 0 111 110 110 0 Z = !Y 2 Y 1 Y 2 = y 2 y 1 + y 2 y 0 + XCKy 1!y 0 Non Max 01 11 10 000 000 001 000 --- 011 001 0 011 011 010 010 000 110 010 1 100 - 000 - - 0 101 - 100 - - 0 111 101 --- 111 0 111 110 110 0 Z = !Y 2 Y 1 Y 2 = y 2 y 1 + y 2 y 0 + XCKy 1!y 0 43

Y 1 Max Y 2 Y 1 Y 0 X, CK 00 01 11 10 Non Max Y 2 Y 1 Y 0 000 000 001 000 011 001 0 011 011 010 010 000 110 010 1 100 - 000 - - 0 101 - 100 - - 0 111 101 110 0 111 110 110 0 X, CK 00 01 11 10 000 000 001 000 --- 011 001 0 011 011 010 010 000 110 010 1 100 - 000 - - 0 101 - 100 - - 0 111 101 --- 111 0 111 110 110 0 Y 1 = Xy 1 + !y 2 y 1 y 0 + y 2 y 1!y 0 + !CKy 1 + XCK!y 2 y 0 Y 1 = Xy 1 + CK!y 2 y 0 + y 2 y 1!y 0 + !CKy 1 44

Max X, CK 00 Y 2 Y 1 Y 0 000 Y 0 01 11 10 000 001 0 Non Max X, CK 00 Y 2 Y 1 Y 0 000 01 11 10 000 001 000 011 001 000 --- 011 001 0 011 011 010 1 010 010 000 110 010 1 100 - 000 - - 0 101 - 100 - - 0 111 101 110 0 111 101 --- 111 0 110 111 110 110 110 0 Y 0 = X!y 1 y 0 + !X!CKy 2 + X!CK!y 1 + CK!y 2 y 1 y 0 + !Xy 2 y 1 y 0 Y 0 = CK!y 2 y 0 + !X!CKy 2 + X!CK!y 1 + y 2 y 1 y 0 45

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VHDL program representing the transition table (with races) entity Solution is Port ( Reset : Input : Clock : Output : State : -- in in in out inout STD_LOGIC; STD_LOGIC_VECTOR(2 DOWNTO 0) ); 8 states Non Max X, CK 00 Y 2 Y 1 Y 0 000 01 11 10 000 001 000 --- 011 001 0 011 011 010 010 000 110 010 1 if (Reset ='1') then state <= "000"; else 111 000 --- 111 0 case state is when "000" => 110 111 110 110 0 end Soluzione; architecture Behavioral of Solution is begin mono: process (Reset, Input, Clock, State) begin if (Input ='1' and Clock ='0') then state <= "001"; end if; when "001" => if (Input ='0' and Clock ='0') then state <= "000"; elsif (Input ='1' and Clock ='1') then state <= "011"; end if; when "011" => if Clock = '0' then state <= "010"; end if; 47

when "010" => if (Input ='0' and Clock = '1') then state <= "000"; elsif (Input ='1' and Clock = '1') then state <= "110"; end if; when "110"=> if (Input ='0' and Clock = '0') then state <= "111"; end if; when "111" => if (Input ='0' and Clock = '1') then state <= “ 000" ; end if; when others => null; end case; if (State = "010" or State = "011") then Output<= '1'; else Output <='0'; end if; end process mono; end Behavioral; 48

A music playback device has volume regulation system with three keys ‘+’ , ‘–‘ and ‘■’ whose behaviour is the following; when no key is depressed – ■ + are all 0, and at any time only one key can be depressed. A release of a key and the concurrent depression of another is impossible. - ■ + Design an asynchronous sequential circuit with two outputs I(ncrease) and D(ecrease), used to increase (ID=10) or decrease (ID=01) the volume. • If the volume must not be regulated or the as soon as ‘■’ key is depressed the volume must not change. • When the +’ ( ‘–‘) key is depressed the volume must be increased (decreased) upon the release of the key. The increase (decrease) of the volume stops either when the +’ ( ‘–‘) is released after being depressed again or as soon as ‘■’ is depressed. • If ‘–‘ (+) is depressed while the volume increases (decreases) the volume change is stopped immediately and is reversed as soon as ‘–‘ (+) key is released 49

Surely a simmetrical state diagram! 100, 00 - key depressed 100, 00 F -■+, ID 000, 00 + key depressed 001, 00 A 001, 00 B 000, 0100, -0 - key released Volume decrease H 100, 01 G - Volume decrease immediate stop 100, 01 key depressed again - Ready to stop volume change 000, 01 010, 0■ Key depressed Volume decrease Immediate stop 000, -0 + key released 001, 0010, 00 000, 0 - E 010, 00 Here the output is a «don’t care» because it does not matter when the output changes Volume decrease immediate stop 010, -0 ■ Key depressed Volume increase Immediate stop Volume increase 000, -0 D C 001, 10 + key depressed 001, 10 000, 10 again - Ready to stop volume change • If the volume must not be regulated or as soon as when the ‘■’ key is depressed the volume must not change • When the +’ ( ‘–‘) key is depressed the volume must be increased (decreased) upon the release of the key. The volume increase (decrease) stops either when the +’ ( ‘–‘) is released after being depressed again or as soon as ‘■’ is depressed. • If ‘–‘ (+) is depressed while the volume increases (decreases) the volume change must sbe reversed as soon as – ‘ ‘ (+) key is released 50 Vivado Volume_regulator

X 1 = X 2 = ■ X 3 = + 000 001 010 101 110 A A, 00 B, 00 -, - B C, -0 B, 00 -, - -, - C C, 10 D, 10 -, - E, -0 F, -0 -, - D D A, -0 D, 10 -, - -, - E -- AC -- E A, 00 -, - E, 00 -, - F AG CG AG F G, 0 - -, - -, - AC G G, 01 B, 0 - -, - -- -- H A, 0 - -, - E, 00 F, 00 -, - B E, 0 - F, 00 -, H, 01 -, - AC C AC G H A -, - H, 01 -, - AG B C D E AG F G -, - Maximal compatibility classes [AE], [B], [C], [DEH], [F], [G] For the coverture all of them are necessary But could I leave A alone ? 51

X 1 = X 2 = ■ X 3 = + 000 001 011 010 100 101 111 110 A A, 00 B, 00 -, - E, 00 F, 00 -, - B C, -0 B, 00 -, - -, - [AE] => a a, 00 b, 00 -, - a/d, 00 f, 00 -, - C C, 10 D, 10 -, - E, -0 F, -0 -, - [B] => b c, -0 b, 00 -, - D A, -0 D, 10 -, - -, - [C] => c E A, 00 -, - E, 00 -, - [DEH] => d F G, 0 - -, - F, 00 -, - [F] G G, 01 B, 0 - -, - E, 0 - H, 01 -, - [G] H A, 0 - -, - H, 01 -, - [AE] [B] [C] [DEH] [F] [G] => => => -, - -, - c, 10 d, 10 -, - a/d, -0 f, -0 -, - a, 00 d, 10 -, - a/d, 00 d, 01 -, - => f g, 0 - f, 00 -, - => g g, 01 b, 0 - -, - a/d, 0 - d, 01 -, - -, - a b c d f g 52

X 1 = X 2 = ■ X 3 = + 000 001 010 101 110 [AE] => a a, 00 b, 00 -, - a, 00 [B] => b c, -0 b, 00 -, - [C] => c c, 10 d, 10 -, - [DEH] => d a, 00 d, 10 -, - [F] => f g, 0 - [G] => g g, 01 b, 0 - -, - f, 00 -, - X 1 = X 2 = ■ X 3 = + y 3 y 2 y 1 000 001 010 101 110 -, - a 000, 00 001, 00 -, - b 001 011, -0 001, 00 -, - a, -0 f, -0 -, - c 011, 10 a, 00 d, 01 -, - d 010 -, - f, 00 -, - a, 0 - d, 01 -, -, - 000, 00 -, - 100, 00 -, - -, - 000, -0 010, 10 -, - 010, -0 100, -0 -, 111, -0 -, - 000, 00 010, 10 -, - 010, 01 -, - f 100 101, 0 - -, - 000, 0 -, - 100, 00 -, - g 101, 01 001, 0 - -, - 100, 0000, 0 - 010, 01 -, - 000, 00 -, - 111 -, - -, -, 110, -0 -, - 110 -, - -, 100, -0 -, - No way with this coding Find alternative coding!! 53

Can we transform a Moore table into a Mealy table? X 1 X 2 A Moore X 1 X 2 00 01 11 10 B A A A 0 B B C A A 0 C A C D A 0 D A A D A 1 X 2 Let’s associate to each transition the output value of the destination state (or of the source state) Mealy 00 01 11 10 A B, 0 A, 0 B B, 0 C, 0 A, 0 C, 0 D, 1 A, 0 D, 1 A, 0 Mealy 00 01 11 10 A B, 0 A, 0 B B, 0 C, 0 A, 0 C, 0 D, - D A, - A, 0 D, 1 A, - Obviously in the transitions the outputs can be don’t care if we are not interested whether the network anticipates or delays the outputs 54

Can we transform a Mealy table into a Moore table? X 1 X 2 Mealy X 1 X 2 00 01 11 10 A B, 1 A, 0 A, 1 B B, 1 C, - A, 1 A, - C A, 1 C, 0 D, 1 A, 0 D A, - A, 0 D, 1 A, 1 X 2 Same state with different ouptuts. The state must be doubled Moore 00 01 11 10 A 0 B A 0 A 1 B A 0 A 1 1 B B C A 1 1 C A 1 C D A 0 0 D A 1 A 0 D A 1 1 Stable output 1 00 01 11 10 A 0 B A 0 A 1 B A 0 A 1 1 B B C A 1 1 C A 1 C D A 1 0 D B A 0 D A 1 1 Multiple transitions Removed 55

A particular synthesis - 1 Design an asynchronous sequential network whose output Z assumes the value of the input D upon the positive transition (sampling) of an input C(lock). The output is stable until C samples a different input. (Obviously a symmetrical diagram) 00 01 G, 0 00 01 D 11 B, 0 10 DC 10 C, 0 00 A zero is sampled: the output changes 01 F, 1 00 01 11 10 A G A B --- 0 B --- A B C 0 C G --- D C 0 D --- E D H 1 E F E D --- 1 F F A --- H 1 G G A --- C 0 H F --- D H 1 11 01 A, 0 C 10 00 00 E, 1 00 01 11 D, 1 11 01 10 A one is sampled: the output changes 11 H, 1 10 11 Blue states => output 0 stable Red states => output 1 stable Yellow states are the only states from where an output change can occur 10 56

D D y 1 C 00 01 11 10 A G A B --- 0 B --- A B C 0 C G --- D C 0 D --- E D H 1 E F E D --- 1 F F A --- H 1 G G A --- C 0 H F --- D H 1 C y 2 A particular synthesis - 2 --- C BD BD D E --- F AE AE --- --- D E F G --- --- H A D 00 01 11 10 B B C G Here we don’t use the maximal compatibility classes but coverture and closure are verified C 00 01 11 10 00 00 01 0 a a b 0 01 00 -- 11 01 0 b a -- g b 0 11 11 11 1 g d g g g 1 10 10 00 -- 11 1 d d a -- g 1 [ABG] [C] [DEH] [F] => => a b g d 57

A particular synthesis - 3 D y 1 C y 2 00 01 11 10 a 00 00 01 b 01 00 -- 11 01 0 g 11 10 11 11 11 1 d 10 10 00 -- 11 1 0 Y 1= Y 2 C + Y 1!C Y 2= Y 2 C + D!C Z = Y 1 D(elay) Flip Flop – The D name will be explained later - The arrows indicate the output variations It is the only FF used in the synchronous networks NB: The correct behaviour takes for granted obviously (as is the case with all asynchronous networks) that the input D is stable during the transition 0 to 1 of the C(lock) (b->g and d->a) which means the a little time t 1 (setup time) before the C transition and t 2 (hold time) after the C transition D must be stable. t 1 and t 2 values depend on the technology. If this condition is violated the output behaviour is unpredictable (aliasing - metastability) 58

Y 1=Z !Z How must this circuit be modified in order to insert two inputs Reset (Z=0) and Preset (Z=1)? Notice that if both true and inverted values of the output an inverter should be added. BUT in this case the two outputs wouldn’t be synchronous 59

D Flip-Flop D Q DFF CK CK FFD: An asynchronous sequential network whose output Q copies the logical value of D input during the rising edges (positive edge triggered) of input CK CK D No change without ck Q The FFD is typically used as memory elementary cell in the synchronous sequential networks (see later). In that case CK signal normally (but not necessarilty) has a periodical waveform (clock). 60

Correct use of DFF Setup (t. SU), Hold (t. H) and Answer (t. R) times D Q DFF CK CK CK D Q t. SU t. H t. R The behaviour is correct only if t. SU≥ t. SUmin and t. H ≥ t. Hmin, otherwise metastability. 61

Metastability t. SU t. H CK D Q 1 Q 2 Q 3 Unpredictable and non-repetitive behaviour 62

D type FF 7474 As is the case with all FFs it is required that both true and inverted outputs are available at the same time. To this end in pratice the DFF is synthesized with a redundant coding using three state variables (R, S e Q) with the following schematic CP=CK 63

Edge Triggered DFF with SET and PRESET !Asynchronous Set !Asynchronous Reset Obviously both !S and !R must not be 0 concurrently (what happens in this case ? ) 64

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Analysis … three state variables S R Q If SR=0 (!S+!R=1) Q and !Q are complementary Her e!S is indicated as S and !R as R Asybchronous Set and missing C D Not reachebale or instable C=1 C=0 00 01 11 10 000 --- --- 001 --- --- 011 111 011 010 --- --- 100 110 100 101 -- -- 111 111 011 100 110 110 011 100 SRQ C X Only stable states S=R=0 and Q any value is unstable (S=0 => R=1 ) S= 0 R=1 and Q=0 is impossible (S=0 implies Q=1) NB: Here X is not equal to !R (S=0 R=1 D=0 -> X=1) Q switch S= 1 R=0 e Q=1 is impossble (R=0 implies Q=0) If C=0 ->S=R=1 and then Q stable (in green) If S=0 (=> R=1) e C=1 Q=1 and D has no impact (row 011 right comlumns-> S is stable independently from X). If C=0 the future state is 111 (S=R=1) and Q does not change Row 111. With C=0 S=R=1 and Q is stable If C becomes 1 with D=1 X=0 and then R remains 1 and only S changes which becomes 0 (therefore Q=1). If D=0 X=1 and with C=1 R becomes 0 (while S remains 1) and therefore !Q=1 and Q=0. Similar behaviour for row 110 First level FFs are NOT SR (the outputs are not complementary) The first two columns with C=0 lead potentially to a possible Q transition (C=0) The last two columns with C=1 do NOT lead potentially to a possible Q transition (C=1) 70

C D 00 01 11 10 000 --- --- 001 --- --- A 011 111 011 010 --- --- B 100 110 101 -- -- C 111 -- D 110 “De-synthesizing” … SRQ C D 00 01 11 10 A 011 C, 1 A, 1 B 100 D, 0 B, 0 100 C 111 C, 1 -- C, 1 A, 1 B, 0 -- -- D 110 D, 0 A, 1 B, 0 111 011 100 110 011 100 00 01 11 10 A 00 10, 1 00, 1 Le frecce indicano le transizioni di Q C D 00 01 11 10 Y 2 Y 1 A 00 10, 1 00, 1 B 01 11, 0 01, 0 D 11 11, 0 10, - 01, 0 D 11 11, 0 00, - 01, 0 C 10 10, 1 -- 10, 1 00, 1 11, - C 10 10, 1 -- 10, 1 01, - Multiple transitions Critical races! 71

Synthesis… C D 00 01 11 10 10, 1 00, 1 y 2 y 1 A 00 Y 1 = !Cy 1 + !y 2 y 1 B 01 11, 0 01, 0 D 11 11, 0 10, - 01, 0 C 10 10, 1 -- 10, 1 00, 1 11, - Y 2 = !C + C!Dy 2 + !Dy 2!y 1 + Dy 2 y 1 Z = !y 1 But y 2 is not the complement of y 1: it is not a FF in strict sense 72

Re-syntehesizing… C D 00 01 11 C D 10 SRQ 00 01 11 10 000 --- --- 001 --- --- 011 111 011 010 --- 011 --- SRQ 000 --- --- 001 --- --- 011 111 011 010 --- --- 100 110 100 101 -- -- 100 110 100 111 -- 111 011 100 101 -- -- -- 100 110 110 011 100 111 -- 111 011 101 110 110 010 100 --- Races removal Unused! Races S = !C + !DS + S!R = !C + S(!R + !D)= !C +S !(RD) =!(C !(S !(RD))) R = !C + !S + RD = !(C S !(RD)) Non minimal synthesis Q = !S + RQ = !(S !(RQ)) C S = !C + !DS + S!R = !C + S(!R + !D)= !C +S !(RD) =!(C !(S !(RD))) R = !C + !S + RD = !(C S !(RD)) Q = !S + RQ = !(S !(RQ)) 73

7474 – Schematic 2 74

CD Latch C Q C S Q* D Q Q* Q* SR CD D Q Q* C D Q Q* 0 0 Q Q* 0 1 Q Q* 1 0 0 1 1 0 R D C D Q t. SU t. H t. SU ≥ t. SUmin t. H≥ t. Hmin Response time t. R = t. SU+ t. H Constraints: How would you implement a Latch from a state table or a DFF with a two inputs MUX ? 75

CD Latch DC 01 11 01 A, 0 11 00 01 10 E, 0 B, 1 11 11 10 C, 0 D, 1 00 10 00 F, 1 10 00 D 10 C 00 01 11 10 A C A B --- 0 B --- A B D 1 C C A --- E 0 D D F A --- D 1 E E C --- B E 0 F F F A --- D 1 B C D 00 C [ACE] [BDF] a b --- ----- --B C D E 00 01 11 10 a a a b a 0 b b a b b 1 D y --- A 01 C 00 01 11 10 0 1 1 1 Y= CD + !Cy With SR ? 76

CD Latch 1 D Q D 0 S Mux O Q DFF CK CK 77

373 74 XX 373 D 0 00 D 1 O 1 D 2 O 2 D 3 O 3 D 4 O 4 D 5 O 5 D 6 O 6 D 7 O 7 CK OE* 8 bit Latch register 3 -state outputs OE* CK C Qi Oi Latch CD Di D CK Di Qi OE* Oi Z 78

374 74 XX 374 D 0 00 D 1 O 1 D 2 O 2 D 3 O 3 D 4 O 4 D 5 O 5 D 6 O 6 D 7 O 7 CK OE* 8 bit Edge-Triggered register 3 -state outputs OE* Qi CK Oi Flip-Flop D Di D CK Di Qi OE* Oi Z 79

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Exercise The control of a sliding gate is based on an asynchronous sequential machine with three input signals (S, T, P) and two output signals (A, C) • S=1 is a key indicating whether the gate is fully open or fully closed • T is a telecontrol: T=1 orders to the machine to keep the gate open (if it is already) or to open it • P is a photocell with detects obstacles on the gate: P=1 orders to the machine to keep the gate open (if it is already) or to open it • T=P=0 condition triggers the closure of the gate • A=1 and C=0 opens the gate • A=0 and C=1 closes the gate • A=0 and C=0 keeps the gate stopped either fully closed or fully open

Gate closed 1, 1, 0, 0 1, 0 Telecontrol reactivated N closed Telecontrol deactivated 0, 0, 0 1, 0 0, 1, 0 Telecontrol 0, 1, 0 1, 0, 0 1, 0 Telecontrol activation 1, 1, 0 B closed C Telecontrol M Opening obstacle Telecomando 1, 1, 0 0, 0 1, 0, 0 0, 1 Obstacle telecontrol 0, 1, 0 Telecontrol 1, 1, 0 0, 0 D Open tlc Ostacle Telecontrol 1, 1, 0 0, 0 No obstacle telecontrol 0, 0, 0 0, 1 0, 0, 0 Closure 1, 0 0, 1 1, 0, 0 0, 1 Open No telecomando 1, 1, 1 0, 0 H G 1, 1, 0 0, 0 Telecontrol reactivated 0, 0, 0 0, 1 closure 0, 1, 0 Motion end 1, 0, 0 0, 1 E Open tlc obstacle 1, 1, 1 0, 0 open tlc onstacle No telecontrol no obstacle ! Obstacle I Gate open Obstacle Open obstacle Obstacle telecontrol 0, 1, 1 1, 0, 1 0, 0 F 1, 1, 1 0, 0 1, 0, 1 0, 0, 1 1, 0 Obstacle Open 1, 0, 1 Obstacle 0, 0 1, 0, 0 No obstacle 0, 1 1, 1, 1 0, 0 L A=C=0 keeps open or closed A=1 open C=1 ccloses Once the telecontrol is activated the gate reaches a full open state and then immediately closes again with no telecontrol and no obstacle (which on the contrary trigger the reopening or keep the gate open) Closed gate No motion 1, 0, 0, 1 1, 0 Stato I Telecontrol Opening tlc 0, 1, 1 1, 0 A End position 0, 0, 0 1, 0 0, 1, 0, 0 A, C 0, 0 closed 0, 0, 0 1, 0 No telecontrol S gate open or closed sensor T Telecontrol open gate P Obstacle detected S, T, P 1, 0, 1 0, 0 Obstacle only 0, 1, 1 1, 0 0, 0, 1 1, 0 Obstacle telecontrol

S sensore S disattivo T P sensore S attivo 000 001 010 101 110 A -, - B -, - C M, 10 -, - D -, - G, 01 -, - E -, - -, - F -, - G, 01 F, 00 E, 00 -, - F => gate open and obstacle => telecontrol inactive. Gate starts closing if obstacle removed G H, 01 -, - G, 01 F, 00 -, - D, 00 G => gate open -=> closure if telecontrol inactive and no obstacle H H, 01 I, 10 -, - H => gate closing - reopening if telecontrol or obstacle F, 00 -, - I => obstacle =>. If obstacle removed closure I -, - C, 10 N, 10 -, - L, 10 C, 10 -, - M M, 10 I, 10 -, - N M, 10 -, - I, 10 -, - L, 10 C, 10 -, - B, 10 A and B => gate closed – obstacle not possible: A => sensor S inactive not possible -, - B, 10 B => telecontrol active – gate about to open to the end -, - D, 00 E, 00 D, 00 F, 00 E, 00 D, 00 C, 10 A, 00 -, - H, 01 I, 10 L, 10 -, - L A, 00 -, - E, 00 -, - C => gate opening with telecontrol until S active. If the telecontrol is released the gate opens anyway to the end D => gate fully open => telecontrol active attivo D => sensor S inactive not possible E => gate open with obstacle and telecontrol active. If telecontrol released gate stopped because of obstacle and the same if ostacle removed L => gate opening with telecontrol active and obstacle C, 10 G, 01 -, - M => gate opening with telecontrol inactive. When fully open if no telecontrol and no obstacle closure -, - N, 10 -, - B, 10 N => gate still closed. (obstacle impossible) but telecontrol activated and released. Gate opens to the end

S sensore S disattivo T P sensore S attivo 000 001 010 101 110 A -, - B -, - C M, 10 -, - D -, - G, 01 -, - E -, - -, - F G H I -, - H, 01 -, - C, 10 N, 10 -, - L, 10 C, 10 -, -, - A, 00 -, - -, - B, 10 B CD -- E -- -- -, - B, 10 -, - D, 00 F E, 00 D, 00 G F, 00 E, 00 D, 00 G, 01 F, 00 E, 00 -, G, 01 F, 00 -, - D, 00 -- H -- I -- -- L -- -- M H, 01 I, 10 -, - C, 10 A, 00 -, - H, 01 I, 10 L, 10 -, - F, 00 -, - L -, - M M, 10 I, 10 -, - C, 10 G, 01 -, - N M, 10 -, - N, 10 -, - B, 10 I, 10 L, 10 C, 10 -, - E, 00 -, - -- -- -- -- -- N A B -- C D E F G H I L M Non maximal compatibility classes closed and covered [AHIL] [CDEFM] [BN] [G] a b g d

S sensore S disattivo T P sensore S attivo 000 001 010 101 110 A -, - B -, - C M, 10 -, - D -, - C, 10 N, 10 -, - L, 10 C, 10 -, - A, 00 -, - G, 01 -, - B, 10 -, - D, 00 -, - -, - F -, - G, 01 F, 00 E, 00 -, - H I L H, 01 -, - T P Y 1 Y 0 E, 00 D, 00 E G [AHIL] [CDEFM] [BN] [G] a b g d 00 01 11 10 F, 00 E, 00 D, 00 G, 01 F, 00 -, - D, 00 C, 10 A, 00 -, - H, 01 I, 10 L, 10 -, -, - I, 10 L, 10 C, 10 -, - M M, 10 I, 10 -, - N M, 10 -, - 11 10 00, 01 00, 10 01, 10 01 01, 10 00, 10 01, 10 11 01, 10 -, - 10 00, 01 -, - 11 10 S=0 T P Y 1 01 00 Y 0 H, 01 I, 10 -, - 00 00 01 -, - 00 00, 00 01, 00 11, 10 F, 00 -, - 01 01, 00 11 11, 10 10 10, 01 01, 00 -, - E, 00 -, - C, 10 G, 01 -, - N, 10 -, - B, 10 -, - 11, 00 -, - 01, 00 S=1

T P Y 1 Y 0 00 11 10 00 00, 01 00, 10 01, 10 01 01, 10 00, 10 01, 10 11 01, 10 -, - 10 00, 01 -, - 11 10 -, - S=0 T P Y 1 01 Y 0 00 01 00 00, 00 01, 00 11, 10 01 01, 00 11 11, 10 10 10, 01 01, 00 -, - 11, 00 -, - 01, 00 S=1 Race requiring multiple transitions Critical races: add states

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