ASICS Status Ivan Peri University of Heidelberg Germany

ASICS - Status Ivan Perić University of Heidelberg Germany 1

ASICs on the module DHP DCE DCD SWITCHER 2

SWITCHERB • • Three SWITCHER versions have been designed SWITCHERB in 350 nm AMS technology (tested) SWITCHERB 18 in 180 nm AMS technology (tested) SWITCHERB 18 G (“G” for gated-mode) in 180 nm AMS (submitted in May) All three chips are pin- and control-signal- compatible to each other SWITCHERERB 18 G is an extended SWITCHER version that supports the gated-mode operation We have designed a probe station based needle card system for serial tests Yield is about 80% (both tested versions) 3

SWITCHERB and SWITCHERB 18 SWITCHERB in 350 nm AMS (radiation tolerant layout) SWITCHERB 18 in 180 nm AMS (standard layout) 4

SWITCHERB - Plans • • • Will be done soon: Irradiations of SWITCHERB 18: SWITCHERB in 350 nm has been layout-ed in the rad-hard “fashion” i. e. with enclosed gatetransistors SWITCHERB 18 uses only the standard layout – due to a thinner gate oxide we expect a sufficient radiation tolerance without the rad-hard layout DCDB (in 180 nm UMC technology) also uses the standard layout in its digital part September 2012 – testing of the gated mode in test beam Bumping issues: So far we use the gold+solder- bump technique developed in HD We will check the possibility to use a commercial bumping The final chip will require only small changes 5

DCD • • • The second version of DCDB (DCDBv 2) has been tested at the full speed stand alone and with PXD (100 ns sampling rate) The chip has been successfully used in several test beams, mostly at a reduced speed due to FGPA issues The typical noise is around 60 n. A – assuming realistic DEPFET gq about: 120 e The analog mode common mode correction (ACMC) is still under investigation – different bump/wire-bond adapters are needed for these tests - complicated First results (ACMC) with a small size test chip are good We have designed a probe-station-based needle card system for serial tests The card uses special soft needles for bumped chips Yield is about 80% (DCDBv 2) We do not observe broken channels – about one per cent of the channels are somewhat more sensitive to the bias settings than the “good channels”, not an serious issue 6

DCD • DCD test at 100 MHz Characteristics of 256 ADCs 260 n. A Average noise ~ 60 n. A (noise on standard PCB ~ 40 n. A) 180 n. A 7

Hybrid Board with DCDBv 2 and thin PXD at full speed • • The histogram of all pixel amplitudes – the signal dispersion is an (overestimated) measure of noise RMS: 1. 5 ADC units (about 80 n. A) Cluster signal is a bit overestimated due to a bug (fixed later) Realistic value for cluster signal ~ 40 ADC units – SNR 26 Preliminary!!! 8

DCD - Plans • • • Irradiation of DCDBv 2 is planned with Bonn. We have already irradiated the first DCD prototype with almost identical analog parts – we do not expect any “surprises” The final version requires several non-complicated changes: Replacing of the standard memory cells with the SEU tolerant cells in the global configuration register Adding of the read-back possibility to monitor SEU rate Adding of an additional offset correction in the analog channels to cope with DEPFET mismatch Implementing of a test multiplexer to allow probe-station tests of the entire chip (only ½ of the channels can be tested presently!) Implementing of a temperature-stable reference current generator Minor layout changes for better yield (should eliminate sensitive channels) Amplifier gain should be adjusted to achieve a higher dynamic range (the gain is programmable) Minor changes in the ACMC network Optionally – implementation of power regulators for Amp. Low and Ref. In voltages – the regulators will be tested soon – they are implemented on a smaller test chip that we already received 9

DHP • • • • • DHP in IBM 90 nm The full-size DHP chip (DHP 0. 2) has been designed in 90 nm IBM technology The chip has been successfully tested (without DCD): Successful data transmission through a 15 m cable at 1. 6 GBit/s Data processing works: pedestal subtraction, CM correction, hit finding… SWITCHER sequencer tested The next step: Tests with DCD and DHP together DHPT in TSMC 65 nm Since IBM has stopped offering the technology for small customers, DHP will be redesigned in 65 nm TSMC technology Three DHP test chips in 65 nm TSMC have been investigated Chip A: PLL and CML Chip B: RAM Chip C: DAC and Reference PLL and CML work - successful transmission at 16 GBit/s through 10 -15 m cable RAM has been tested and irradiated at CERN PS to check SEU tolerance SEU x-section for RAM estimated ~ 10 -13 cm-2 for 24 Ge. V protons We expect 104 neutrons/cm 2 s from background -> if we assume 106 bits in total, we will have a flip every 15 minutes – can be coped easily Chip works up to very high doses ~ 800 MRad (!) Full size chip (DHPT 1. 0, TSMC 65 nm) should be designed & submitted by end 2012 10

DHP DHH emulator DHP 0. 2 on WB adapter DHPT chips DUT DHP 0. 2 Test system DHP 0. 2 Eye diagram DHPT in test beam 11

DCE • • DCE 3 minichip (TSMC 65 nm) with 256 clustering nodes back from production Bonding adapter ready Clustering carrier board (CCB) will be ready in September (design finished – the board is in production) CCB uses 2 low cost FPGA connected via 2 serial links (Aurora) to the DHH 14(!) layer PCB DDR 3 socket for DCE 3 board (8 layers) DCE-adapter will be directly bonded to the DCE board CCB firmware (FPGA, monitoring C) development started with DHH-CCB simulation model CCB 12

SWITCHERB 18 G for gated-mode operation • • SWITCHERB 18 G that supports gated-mode operation has been designed in May and will be back from production beginning of September 2012 The chip is pin- and signal-compatible to the standard SWITCHER versions In standard mode operation the equal signal sequence is used as presently Gated-mode operation requires a slightly modified sequence 13

SWITCHERB 18 G block schematic • • • 32 high-voltage channels (level shifters) that generate the high-voltage signals. Low voltage control block (based on shift register) used to select the high-voltage channels. Two voltage regulators that generate 4 high-voltage supplies each Fast control uses four signals: CLK, Sin, Str. Gate, Str. Clear Gated mode control Gated-mode control FF Volt. Regulator SEROUT Noisy. En 3 FF LV Ctr. HV Chan. FF JTAG Slow control FF Str. GB Noisy. En 0 CLK SERIN STRG STRC GHi, GLo CHi, CLo CCLK or Str. Clr 14

SWITCHERB 18 G • • The channels are divided into 4 groups, 8 channels each These groups enter the gated phase one after another to avoid high clear currents when clear signals are set high The controlling of the SWITCHER is performed using 4 signals: Str. Clr, Str. Gate, CLK and Sin, as presently The activating of the gated phase is initiated by a signal combination that in normal operation does not occur During the gated phase, the LV control logic of the channel operates in a slightly different way than during the normal phase – the control sequence should be slightly adjusted Two gated readout modes are supported Mode 1: Readout doesn’t stop during blind phase Mode 2: Readout is stopped during blind phase 15

Waveforms – readout during blind phase Noisy Seqence Noisy Enable#1 Noisy Enable#2 Str. Clr CLK Str. Gate off gate on on clr Clr 1 clr True reset Blind mode S Bl. mode Clr 3 Gate. On 3 gate Blind mode Gate. On 1 S Clr 2 Gate. On 2 gate S True reset Clr 4 S Gate. On 4 Clr 5 Blind mode S Gate. On 5 Clr 6 True reset Blind mode S Gate. On 6 Noisy Bunches

Waveforms – no readout during blind phase Noisy Seqence Noisy Enable#1 Noisy Enable#2 Str. Clr CLK Str. Gate off on on Clr 1 Blind mode Gate. On 1 S Clr 2 Gate. On 2 Clr 3 Gate. On 3 True reset Blind mode S X A B C S S True reset S Clr 4 Gate. On 4 Clr 5 Gate. On 5 Clr 6 Gate. On 6 Noisy Bunches D S E True reset

SWITCHERB 18 G - layout Volt. Regulator LV ctrl. Bump pads 3625 m LVDS receivers HV channel Prot. Diodes JTAG 1470 m 18

Simulations We simulate the gated mode SWITCHER with readout during blind phase Ch#7 Clr Blind phase Gate On Ch#0 19

Simulations We simulate the gated mode SWITCHER without readout during blind phase Ch#6 Clr Blind phase Gate On Ch#0 Ch#7 20

Simulations of the Module with 6 SWITCHERs 196 SWITCHER channels 256 “ 4 -columns” 196 “ 4 -rows” Source, Gate. Hi/Lo, Clr. Hi/Lo, gnd, vdd 200 Ohm resistors simulate DCDs Decoupling capacitors on the module – all reverenced to source with serial R=0. 25 Ohm Transmission lines – distributed LRC elements – simulates flex 3. 76 ns, 38 Ohm Signal speed: 1/(lc)0. 5 Ideal voltage sources – in reality large decoupling capacitors Impedance: l/c 21

Simplified equivalent circuit of the module 6 x 32 rows row 3. 76 ns, 38 Ohm CCG 10 k. Ohm CCGint Drift Clear. Hi Clear. Lo 25 65 To all (except drain) To all 37 Source Gate. Hi Clear Gate. Lo 200 Ohm Gate Drain

Results 1: Decoupling 10 n. F Drain current Source Dirty Bunch Phase Channel 3 Channel 2 Channel 1 Gate Clear Channel 0

Results 1: Decoupling 10 n. F Signal no plateau Drain current Pedestal Dirty Bunch Phase

Results 1: Decoupling 10 n. F Equal pedestals Signal no plateau Drain current Pedestal Dirty Bunch Phase

Results 2: Decoupling 100 n. F Dirty Bunch Phase Channel 3 Channel 2 Channel 1 Gate Clear Channel 0 Drain current Source

Results 2: Decoupling 100 n. F Signal Better plateau? Drain current Pedestal Dirty Bunch Phase

Results 2: Decoupling 100 n. F Equal pedestals Signal Better plateau? Drain current Pedestal Dirty Bunch Phase

Conclusions • • • New SWITCHERB 18 v 2 that supports gated-mode operation has been designed and submitted The chip will be available beginning of September The full size DHP 0. 2 has been successfully tested without DCD Tests with DCD will be done soon DHPT test chips in 65 nm TSMC technology have been successfully tested as well – RAM, 1. 6 GBit/s data transmission and PLL work. The RAM chip has been irradiated up to 800 MRad to test SEU rate. The SEU tolerance is good and sufficient DCDv 2 works fine Ordering of larger number of DCD chips is relatively cheap - 30 Chips – 2 k€ Preliminary module-level simulations show that gated mode operation is possible DCE boards have been designed and are in production. First tests in September 2012 29

• Backup slides 30

High voltage channel • • • High-voltage channel - main parts: U-I converter C High-voltage power transistors Tp and Tn. Floating-logic gate control blocks. Low power consumption – sleep mode Break before make feature C/GHI gate control block 1. 8 V off C/GHI 0 Tp on VDDD 1. 8 V LV ctrl. HVOut LVIn C Sleep GNDD 0 V C/GLO 0 1. 8 V off on Tn C/GLO 31

Regulator hi 1. 8 hi 0 Power T ref lo 0 Power T 1. 8 sub 1. 8 lo 32

High voltage channel – transistor schematic C/GHI Tonn Tp Tdion Toffp Tdiop Buff 1 Tswn VDDD C/GHI 0 Tdiffn Tdiffp D 2 LVIn HVOut D 1 Idiff C/GLO 0 Tswp GNDD n 1 Tdion 2 Tonp Toffn Buff 2 n 2 Inv 3 n 3 Tn C/GLO 33