ASIC 120 Digital Systems and StandardCell ASIC Design

ASIC 120: Digital Systems and Standard-Cell ASIC Design Tutorial 2: Introduction to VHDL October 19, 2005

Outline • • Summary of previous tutorial HDL design flow Format of a VHDL file Combinational statements – assignments, conditionals, when … else • Sequential statements – processes, if … then … else, case, loops

Summary of Previous Tutorial • Digital Systems • Combinational Logic – NOT, AND, OR, XOR, NAND, etc. – mux, half-adder, full-adder • Sequential Logic – flip-flop/register, shift register, counter – state machines

Hardware Description Languages (HDLs) • HDLs describes in text a digital circuit • Examples – VHDL (we will look at this next time) – Verilog – AHDL – JHDL

Hardware Description Languages (HDLs) • schematics are useful for… – drawing high level diagrams – manually working out simple pieces of logic • HDLs are useful for… – describing complex digital systems • HDLs are not. . . – software programming languages (C, Java, assembly, etc. )

Think Digital • When designing a digital system in VHDL, it is important to remember the relation between code constructs and actual hardware

HDL Design Flow 1. 2. 3. 4. 5. 6. 7. Concept, requirements analysis High level design Functional implementation (need not be synthesizable) Functional simulation (3 -> 4 until functionality is good) Synthesizable implementation Synthesizable simulation (6 -> 5 until functionality is good) Timing simulation (7 -> 5 until timing is good; this step I often bypassed in practice) Synthesis 8. • • • 9. design is compiled to hardware we will cover this in more detail later 8 -> 5 if design doesn’t compile or doesn’t fit Testing in hardware (9 -> 5 if something is wrong)

What does “synthesizable” mean? • Synthesizable means that a given design can be compiled into hardware – FPGA (reprogrammable ASIC) – ASIC • A non-synthesizable design can be simulated in software and is useful for – working out functionality – testing out concepts – test benches (covered in detail later)

Levels of Abstraction • Behavioural • Dataflow • Structural

Components of a VHDL File • library – ieee, etc. • use • entity – defines the interface • architecture – defines the functionality • component – reusable functionality • multiple entity/architectures in one file

Why do we use IEEE libraries? • standard VHDL libraries are limited to two values: 0 and 1 • this is fine for theory, but in practice a physical wire can have other values • more on this in later tutorials

Inputs and Outputs • • declared in the entity the “pins” of the hardware block can only be input, output, or I/O output pins cannot be read from – for example, if I assign a value to an output pin I cannot “read” that value back in another place – output pins are like black holes in this way

Signals • Signals are the internal “wires” of your design • Can be assigned a value, or have their value read • Signals can be read in multiple places, but assigned in only one place – “cannot have multiple output pins driving a wire”

buses • Provide an easy way to group multiple signals or ports

Combinational Logic • In VHDL: “Concurrent Statements” • Remember: all functionality is defined within architecture block • Order doesn’t matter • Types of concurrent statements – assignments – conditional assignments – processes

Combinational Assignments destination <= source_logic; examples: X <= A AND B; Y <= NOT (A AND B); Z <= A XOR B AND C NOT B;

Conditional Assignments destination <= source_logic_1 when condition_1 else source_logic_2 when condition_2 else source_logic_3; example: X <= A AND B when Sel = “ 00” else NOT (A AND B) when Sel = “ 01” else A XOR B when Sel(0) & Sel(1) = “ 01”

Conditional Assignment: A MUX • Conditional assignments are modelled physically as a multiplexer

Brackets and The & Operator • Brackets – used to reference parts of buses • & Operator – signal concatenation operator – used for constructing buses out of single wire signals, or parts of other buses

Processes • Contain chunks of VHDL code • Can be purely combinational • Most useful for sequential logic – controlled by a clock • processes are executed in parallel, in any order • Processes can optionally be named

Process Statement [process_name: ] process (sensitivity_list) declarations begin sequential_statements end process;

Sequential Logic • In VHDL: “Sequential Statements” • Within a process, statements execute sequentially – important to remember that logic is tied back to underlying hardware

If … Then …Else Statement • Like the concurrent “when … else” statement, modelled as a multiplexer if first_condition then statements elsif second_condition then statements else statements end if;

MUX with an If Statement process(Sel, A, B, C, D) begin if Sel = "00" then Y <= A; elsif Sel = "01" then Y <= B; elsif Sel = "10" then Y <= C; elsif Sel = "11" then Y <= D; end if; end process;

MUX with an If Statement • Note that this mux is a combinational mux – i. e. , not governed by a clock

Clocked Processes • • Or: “Sequential Processes” Consider a “clocked mux”: process begin wait until rising_edge(Clk); if Sel = "00" then Y <= A; elsif Sel = "01" then Y <= B; elsif Sel = "10" then Y <= C; elsif then Y <= D; end if; end process;

Clocked Processes • Statements are essentially executed in series • Important to always keep in mind underlying hardware

Clocked Processes • Consider: process begin wait until rising_edge(Clk); if Sel = ‘ 0’ then Y <= A; else Y <= B; end if; if Sel = ‘ 0’ then Z <= B; else Z <= A; end if; end process;

Case Statement • Alternative to If … Then … Else case control_expression is when test_expression 1 => statements when test_expression 2 => statements when others => statements end case;

Case Statement case Sel is when “ 00” => X <= B; when “ 10” => X <= A; when others => X <= C; end case;

Case Statement • Does not imply a priority, whereas If … Then … Else does • Conditions must be mutually exclusive • Must take care of all possibilities – “others” case is very useful for this – remember: a wire can have more values than just ‘ 0’ and ‘ 1’

Registers • In digital design, a “register” is a general term that refers to a signal that maintains its value between clock cycles • Modelled in hardware as a Flip Flop – usually a simple D Flip Flop • Registered signals appear on the left side of clocked process assignment statements – caveat: has other connotations in processor design

Registers • Consider: process begin wait until rising_edge(Clk); if Sel = "00" then Y <= A; elsif Sel = "01" then Z <= B; end if; end process; • Y and Z will retain their values between clock cycles until explicitly changed

What’s wrong with this? process begin wait until rising_edge(Clk); if Sel = ‘ 0’ then Y <= A; else Y <= B; end if; if Sel = ‘ 0’ then Y <= B; else Y <= A; end if; end process;

What About This? process begin wait until rising_edge(Clk); if Sel = ‘ 0’ then Y <= A; else Y <= B; end if; end process; process begin wait until rising_edge(Clk); if Sel = ‘ 0’ then Y <= C; else Y <= D; end if; end process;

Remember • Always consider the underlying hardware! – ask yourself: what does the VHDL code I’m writing actually represent?

Loop Statements • Loops in VHDL can be broken into two categories – clocked – non-clocked • Note that a loop statement is sequential – must be inside a process

Clocked Loops • Clocked loops are governed by a clock – implies time dependency • Consider: process begin flag_register <= “ 0000”; for i in 0 to 7 loop wait until rising_edge(clock); flag_register(i) <= ‘ 1’; end loop; end process;

Clocked Loops • Time dependency of a clocked loop therefore translates into some sort of state machine – counter – shift register

Non-Clocked Loops • A non-clocked loop implies no time dependency – we trade time for hardware • Consider: process begin flag_register <= “ 0000”; for i in 0 to 7 loop flag_register(i) <= ‘ 1’; end loop; end process;

Non-Clocked Loops • What would the hardware for this look like? • More useful example of non-clocked loop: process begin wait until rising_edge(clock); for i in 0 to 7 loop if (flag_register(i) = ‘ 1’) then output_signal(i) <= ‘ 1’; end if; end loop; end process;

Loops • Clocked loop – time dependent – implies some sort of state machine • Non-clocked loop – replicates hardware – we will see another way to do this later: for…generate, if…generate • Trade off between time (clocked) and area (non-clocked)

Loop Syntax • For Loop • While Loop

For Loop • Declaration of loop counter is included in declaration of loop • Loop counter does not need to take on numeric values

For Loop process(. . . ) begin. . . [loop_name: ] for loop_var in (range) loop -- repeated statements go here end loop [loop_name]; . . . end process;

While Loop • Does not automatically define loop counter process(. . . ) begin. . . [loop_name: ] while (condition) loop -- repeated statements go here end loop [loop_name]; . . . end process;

While Loop process begin wait until rising_edge(Clk); X <= ‘ 0’; while error_flag /= ‘ 1’ and done /= '1’ loop wait until rising_edge(Clk); X <= ‘ 1’; end loop; end process;

Preview of Next Tutorial • Intermediate VHDL – other signal values besides ‘ 0’ and ‘ 1’ – more VHDL data types – if … generate, for … generate – differences between VHDL standards – splitting a VHDL project across multiple files – test benches • time, procedures, variables, file access, etc.

Summary • • Summary of previous tutorial HDL design flow Format of a VHDL file Combinational statements – assignments, conditionals, when … else • Sequential statements – processes, if … then … else, case, loops

UW ASIC Design Team • www. asic. uwaterloo. ca • reference material – Accolade VHDL reference (excellent!): http: //www. acc-eda. com/vhdlref/ • many of today’s examples came from here – Bryce Leung’s tutorials (UW ASIC website) – Mike Goldsmith’s tutorials (UW ASIC website) – your course notes • my contact info: Jeff Wentworth, jswentwo@engmail. uwaterloo. ca