ARQUITECTURA DE COMPUTADORAS II INTERRUPCIONES EN LA IBM

ARQUITECTURA DE COMPUTADORAS II INTERRUPCIONES EN LA IBM PC POLLING (SONDEO) Carlos Canto Q.

ARQUITECTURA DE COMPUTADORAS II INTERRUPCIONES EN LA IBM PC INTERRUPCIONES Carlos Canto Q.

ARQUITECTURA DE COMPUTADORAS II INTERRUPCIONES EN LA IBM PC La IBM PC original uso el controlador de interrupciones 8259. Este permitía que se pudieran generen hasta 8 señales de interrupción ( numeradas de 0 a 7). Estas líneas de interrupción son llamadas líneas de “Interrupt Request” ( requerimiento de interrupción) o IRQ´s Carlos Canto Q.

ARQUITECTURA DE COMPUTADORAS II INTERRUPCIONES EN LA IBM PC A partir de la IBM AT se incluyen 2 controladores de interrupción, donde el segundo controlador (ESCLAVO) está conectado en cascada a la línea de interrupción 2 del primer controlador ( MAESTRO). L a líneas de interrupción del segundo controlador están numeradas de 8 a 15. Debido a este “cascadeo”, la línea de interrupción 2 no está disponible. Sin embargo ; para compatibilidad con la PC original, la línea de interrrupción 2 es conectada a al línea 9 del segundo controlador ( tal que, si un dispositivo en la PC es configurado para la interrupción 2, en realidad éste usa la interrupción 9) Carlos Canto Q.

ARQUITECTURA DE COMPUTADORAS II INTERRUPCIONES EN LA IBM PC 3 FFF Tenemos 1024 localidades de RAM en la parte más baja de la memoria que permiten 256 vectores de interrupción de 4 bytes cada uno. Tabla de vectores de interrupción Vector 0 IPL IPH CSL CSh 0003 0002 0001 0000 TABLA DE VECTORES DE INTERRUPCIÓN Carlos Canto Q. Un vector de interrupción está formado por la dirección ( 2 bytes para CS y 2 bytes para IP) de inicio de la rutina de servicio de la interrupción ISR esto es expresado como: CS: IP

ARQUITECTURA DE COMPUTADORAS II INTERRUPCIONES EN LA IBM PC Entradas del controlador programable de interrupciones PIC 8259 Carlos Canto Q.

ARQUITECTURA DE COMPUTADORAS II INTERRUPCIONES EN LA IBM PC Registro de máscara de Interrupción Carlos Canto Q. The interrupt mask register is an eight bit register that lets you individually enable and disable interrupts from devices on the system. This is similar to the actions of the cli and sti instructions, but on a device by device basis. Writing a zero to the corresponding bit enables that device’s interrupts. Writing a one disables interrupts from the affected device. Note that this is non-intuitive. Figure 17. 1 provides the layout of the interrupt mask register.

ARQUITECTURA DE COMPUTADORAS II INTERRUPCIONES EN LA IBM PC When an interrupt occurs, regardless of source, the 80 x 86 does the following: 1) The CPU pushes the flags register onto the stack. 2) The CPU pushes a far return address (segment: offset) onto the stack, segment value first. 3) The CPU determines the cause of the interrupt (i. e. , the interrupt number) and fetches the four byte interrupt vector from address 0: vector*4. 4) The CPU transfers control to the routine specified by the interrupt vector table entry. After the completion of these steps, the interrupt service routine takes control. When the interrupt service routine wants to return control, it must execute an iret (interrupt return) instruction. The interrupt return pops the far return address and the flags off the stack. Note that executing a far return is insufficient since that would leave the flags on the stack. Carlos Canto Q.

ARQUITECTURA DE COMPUTADORAS II INTERRUPCIONES EN LA IBM PC The PICs interface to the system through four I/O locations: ports 20 h/0 A 0 h and 21 h/0 A 1 h. The first address in each pair is the address of the master PIC (IRQ 0 -7), the second address in each pair corresponds to the slave PIC (IRQ 8 -15 ). Port 20 h/0 A 0 h is a read/write location to which you write PIC commands and read PIC status, we will refer to this as the command register or the status register. The command register is write only, the status register is read only. They just happen to share the same I/O location. The read/write lines on the PIC determine which register the CPU accesses. Port 21 h/0 A 1 h is a read/write location that contains the interrupt mask register, we will refer to this as the mask register. Choose the appropriate address depending upon which interrupt controller you want to use. Carlos Canto Q.

ARQUITECTURA DE COMPUTADORAS II INTERRUPCIONES EN LA IBM PC Int. Num. Address in I. V. T. Description 0 00 -03 CPU divide by zero 1 04 -07 Debug single step 2 08 -0 B Non Maskable Interrupt (NMI input on processor) 3 0 C-0 F Debug breakpoints 4 10 -13 Arithmetic overflow 5 14 -17 BIOS provided Print Screen routine 6 18 -1 B Reserved 7 1 C-1 F Reserved 8 20 -23 IRQ 0, Time of day hardware services 9 24 -27 IRQ 1, Keyboard Interface A 28 -2 B IRQ 2, ISA Bus cascade services for second 8259 B 2 C-2 F IRQ 3, Com 2 hardware C 30 -33 IRQ 4, Com 1 hardware Carlos Canto Q.

ARQUITECTURA DE COMPUTADORAS II INTERRUPCIONES EN LA IBM PC D 34 -37 IRQ 5, LPT 2, Parallel port hardware (Hard Disk on XT) E 38 -3 B IRQ 6, Floppy Disk adaptor F 3 C-3 F IRQ 7, LPT 1, Parallel port hardware 10 40 -43 Video services, see note 1 11 44 -47 Equipment check 12 48 -4 B Memory size determination 13 4 C-4 F Floppy I/O routines 14 50 -53 Serial port I/O routines 15 54 -57 PC used for Cassette tape services 16 58 -5 B Keyboard I/O routines 17 5 C-5 F Printer I/O routines 18 60 -63 Points to basic interpreter in a "real" IBM PC 19 64 -67 Bootstrap loader 1 A 68 -6 B Time of day services Carlos Canto Q.

ARQUITECTURA DE COMPUTADORAS II INTERRUPCIONES EN LA IBM PC 1 B 6 C-6 F Services Ctrl-Break service 1 C 70 -73 Timer tick (provides 18. 2 ticks per second) 1 D 74 -77 Video parameters 1 E 78 -7 B Disk parameters 1 F 7 C-7 F Video graphics 20 80 -83 Program termination (obsolete) 21 84 -87 All DOS services available through this Interrupt 22 88 -8 B Terminate address 23 8 C-8 B Ctrl-Break exit address 24 90 -93 Critical error handler 25 94 -97 Read logical sectors Carlos Canto Q.

ARQUITECTURA DE COMPUTADORAS II INTERRUPCIONES EN LA IBM PC 26 98 -9 B Write logical sectors 27 9 C-9 F Terminate and stay resident routines (obsolete) 28 to 3 F A 0 -A 3 to FC-FF Reserved for DOS 40 to 4 F 100 -103 to 13 C-13 F Reserved for BIOS 50 140 -143 Reserved for BIOS 51 144 -147 Mouse functions 52 to 59 148 -14 B to 164 -167 Reserved for BIOS 5 A 168 -16 B Reserved for BIOS 5 B 16 C-16 F Reserved for BIOS 5 D 174 -177 Reserved for BIOS 5 E 178 -17 B Reserved for BIOS 5 F 17 C-17 F Reserved for BIOS 60 to 66 180 -183 to 198 -19 B Reserved for User programs 67 19 C-19 F Used for EMS functions Carlos Canto Q.

ARQUITECTURA DE COMPUTADORAS II INTERRUPCIONES EN LA IBM PC 68 to 6 F 1 A 0 -1 A 3 to 1 BC-1 BF Unused 70 1 C 0 -1 C 3 IRQ 8, ISA bus Real time clock 71 1 C 4 -1 C 7 IRQ 9, takes the place of IRQ 2 72 1 C 8 -1 CB IRQ 10 (available hardware interrupt) 73 1 CC-1 CF IRQ 11 (available hardware interrupt) 74 1 D 0 -1 D 3 IRQ 12 (available hardware interrupt) 75 1 D 4 -1 D 7 IRQ 13, maths co-processor 76 1 D 8 -1 DB IRQ 14, ISA bus hard disk controller 77 1 DC-1 DF IRQ 15, (available hardware interrupt) 78 to 7 F 1 E 0 -1 E 3 to 1 FC-1 FF Unused 80 to 85 200 -203 to 214 -217 Reserved for basic 86 to F 0 218 -21 B to 3 C 0 -3 C 3 Used by basic F 1 to FF 3 C 4 -3 C 7 to 3 C 4 -3 FF Unused Carlos Canto Q.