ARM COMPUTER ORGANIZATION AND DESIGN The HardwareSoftware Interface

ARM COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface Chapter 2 Instructions: Language of the Computer Edition

n n The repertoire of instructions of a computer Different computers have different instruction sets n n But with many aspects in common Early computers had very simple instruction sets n n § 2. 1 Introduction Instruction Set Simplified implementation Many modern computers also have simple instruction sets Chapter 2 — Instructions: Language of the Computer — 2

The ARMv 8 Instruction Set n n n A subset, called LEGv 8, used as the example throughout the book Commercialized by ARM Holdings (www. arm. com) Large share of embedded core market n n Applications in consumer electronics, network/storage equipment, cameras, printers, … Typical of many modern ISAs n See ARM Reference Data tear-out card Chapter 2 — Instructions: Language of the Computer — 3

n Add and subtract, three operands n n n Two sources and one destination ADD a, b, c // a gets b + c All arithmetic operations have this form Design Principle 1: Simplicity favours regularity n n § 2. 2 Operations of the Computer Hardware Arithmetic Operations Regularity makes implementation simpler Simplicity enables higher performance at lower cost Chapter 2 — Instructions: Language of the Computer — 4

Arithmetic Example n C code: f = (g + h) - (i + j); n Compiled LEGv 8 code: ADD t 0, g, h ADD t 1, i, j ADD f, t 0, t 1 // temp t 0 = g + h // temp t 1 = i + j // f = t 0 - t 1 Chapter 2 — Instructions: Language of the Computer — 5

n n Arithmetic instructions use register operands LEGv 8 has a 32 × 64 -bit register file n n Use for frequently accessed data 64 -bit data is called a “doubleword” n n 32 -bit data called a “word” n n 31 x 64 -bit general purpose registers X 0 to X 30 § 2. 3 Operands of the Computer Hardware Register Operands 31 x 32 -bit general purpose sub-registers W 0 to W 30 Design Principle 2: Smaller is faster n c. f. main memory: millions of locations Chapter 2 — Instructions: Language of the Computer — 6

LEGv 8 Registers n n n n n X 0 – X 7: procedure arguments/results X 8: indirect result location register X 9 – X 15: temporaries X 16 – X 17 (IP 0 – IP 1): may be used by linker as a scratch register, other times as temporary register X 18: platform register for platform independent code; otherwise a temporary register X 19 – X 27: saved X 28 (SP): stack pointer X 29 (FP): frame pointer X 30 (LR): link register (return address) XZR (register 31): the constant value 0 Chapter 2 — Instructions: Language of the Computer — 7

Register Operand Example n C code: f = (g + h) - (i + j); n f, …, j in X 19, X 20, …, X 23 n Compiled LEGv 8 code: ADD X 9, X 20, X 21 ADD X 10, X 22, X 23 SUB X 19, X 10 Chapter 2 — Instructions: Language of the Computer — 8

Memory Operands n Main memory used for composite data n n To apply arithmetic operations n n n Load values from memory into registers Store result from register to memory Memory is byte addressed n n Arrays, structures, dynamic data Each address identifies an 8 -bit byte LEGv 8 does not require words to be aligned in memory, except for instructions and the stack Chapter 2 — Instructions: Language of the Computer — 9

Memory Operand Example n C code: A[12] = h + A[8]; n h in X 21, base address of A in X 22 n Compiled LEGv 8 code: n Index 8 requires offset of 64 LDUR ADD STUR X 9, [X 22, #64] // U for “unscaled” X 9, X 21, X 9, [X 22, #96] Chapter 2 — Instructions: Language of the Computer — 10

Registers vs. Memory n n Registers are faster to access than memory Operating on memory data requires loads and stores n n More instructions to be executed Compiler must use registers for variables as much as possible n n Only spill to memory for less frequently used variables Register optimization is important! Chapter 2 — Instructions: Language of the Computer — 11

Immediate Operands n Constant data specified in an instruction ADDI X 22, #4 n Design Principle 3: Make the common case fast n n Small constants are common Immediate operand avoids a load instruction Chapter 2 — Instructions: Language of the Computer — 12

n n n Given an n-bit number Range: 0 to +2 n – 1 Example n n § 2. 4 Signed and Unsigned Numbers Unsigned Binary Integers 0000 0000 10112 = 0 + … + 1× 23 + 0× 22 +1× 21 +1× 20 = 0 + … + 8 + 0 + 2 + 1 = 1110 Using 32 bits n 0 to +4, 294, 967, 295 Chapter 2 — Instructions: Language of the Computer — 13

2 s-Complement Signed Integers n n n Given an n-bit number Range: – 2 n – 1 to +2 n – 1 Example n n 1111 1111 11002 = – 1× 231 + 1× 230 + … + 1× 22 +0× 21 +0× 20 = – 2, 147, 483, 648 + 2, 147, 483, 644 = – 410 Using 32 bits n – 2, 147, 483, 648 to +2, 147, 483, 647 Chapter 2 — Instructions: Language of the Computer — 14

2 s-Complement Signed Integers n Bit 31 is sign bit n n n 1 for negative numbers 0 for non-negative numbers –(– 2 n – 1) can’t be represented Non-negative numbers have the same unsigned and 2 s-complement representation Some specific numbers n n 0: 0000 … 0000 – 1: 1111 … 1111 Most-negative: 1000 0000 … 0000 Most-positive: 0111 1111 … 1111 Chapter 2 — Instructions: Language of the Computer — 15

Signed Negation n Complement and add 1 n n Complement means 1 → 0, 0 → 1 Example: negate +2 n n +2 = 0000 … 0010 two – 2 = 1111 … 1101 two + 1 = 1111 … 1110 two Chapter 2 — Instructions: Language of the Computer — 16

Sign Extension n Representing a number using more bits n n Replicate the sign bit to the left n n c. f. unsigned values: extend with 0 s Examples: 8 -bit to 16 -bit n n n Preserve the numeric value +2: 0000 0010 => 0000 0010 – 2: 1111 1110 => 1111 1110 In LEGv 8 instruction set n n LDURSB: sign-extend loaded byte LDURB: zero-extend loaded byte Chapter 2 — Instructions: Language of the Computer — 17

n Instructions are encoded in binary n n Called machine code LEGv 8 instructions n n n Encoded as 32 -bit instruction words Small number of formats encoding operation code (opcode), register numbers, … Regularity! § 2. 5 Representing Instructions in the Computer Representing Instructions Chapter 2 — Instructions: Language of the Computer — 18

Hexadecimal n Base 16 n n 0 1 2 3 n Compact representation of bit strings 4 bits per hex digit 0000 0001 0010 0011 4 5 6 7 0100 0101 0110 0111 8 9 a b 1000 1001 1010 1011 c d e f 1100 1101 1110 1111 Example: eca 8 6420 n 1110 1100 1010 1000 0110 0100 0010 0000 Chapter 2 — Instructions: Language of the Computer — 19

LEGv 8 R-format Instructions n opcode Rm shamt Rn Rd 11 bits 5 bits 6 bits 5 bits Instruction fields n n n opcode: operation code Rm: the second register source operand shamt: shift amount (00000 for now) Rn: the first register source operand Rd: the register destination Chapter 2 — Instructions: Language of the Computer — 20

R-format Example opcode Rm shamt Rn Rd 11 bits 5 bits 6 bits 5 bits ADD X 9, X 20, X 21 1112 ten 21 ten 0 ten 20 ten 9 ten 10001011000 two 10101 two 000000 two 10100 two 01001 two 1000 1011 0001 0101 0000 0010 1001 two = 8 B 15028916 Chapter 2 — Instructions: Language of the Computer — 21

LEGv 8 D-format Instructions n address op 2 Rn Rt 11 bits 9 bits 2 bits 5 bits Load/store instructions n n opcode Rn: base register address: constant offset from contents of base register (+/- 32 doublewords) Rt: destination (load) or source (store) register number Design Principle 3: Good design demands good compromises n n Different formats complicate decoding, but allow 32 -bit instructions uniformly Keep formats as similar as possible Chapter 2 — Instructions: Language of the Computer — 22

LEGv 8 I-format Instructions opcode 10 bits n 12 bits Rn Rd 5 bits Immediate instructions n n n immediate Rn: source register Rd: destination register Immediate field is zero-extended Chapter 2 — Instructions: Language of the Computer — 23

Stored Program Computers The BIG Picture n n n Instructions represented in binary, just like data Instructions and data stored in memory Programs can operate on programs n n e. g. , compilers, linkers, … Binary compatibility allows compiled programs to work on different computers n Standardized ISAs Chapter 2 — Instructions: Language of the Computer — 24

n n Instructions for bitwise manipulation Operation C Java LEGv 8 Shift left << << LSL Shift right >> >>> LSR Bit-by-bit AND & & AND, ANDI Bit-by-bit OR | | OR, ORI Bit-by-bit NOT ~ ~ EOR, EORI § 2. 6 Logical Operations Useful for extracting and inserting groups of bits in a word Chapter 2 — Instructions: Language of the Computer — 25

Shift Operations n n Rm shamt Rn Rd 11 bits 5 bits 6 bits 5 bits shamt: how many positions to shift Shift left logical n n n opcode Shift left and fill with 0 bits LSL by i bits multiplies by 2 i Shift right logical n n Shift right and fill with 0 bits LSR by i bits divides by 2 i (unsigned only) Chapter 2 — Instructions: Language of the Computer — 26

AND Operations n Useful to mask bits in a word n Select some bits, clear others to 0 AND X 9, X 10, X 11 X 10 00000000 000000001101 11000000 X 11 00000000 00000000 00111100 0000 X 9 00000000 000000001100 0000 Chapter 2 — Instructions: Language of the Computer — 27

OR Operations n Useful to include bits in a word n Set some bits to 1, leave others unchanged OR X 9, X 10, X 11 X 10 00000000 000000001101 11000000 X 11 00000000 00000000 00111100 0000 X 9 00000000 00000000 00111101 11000000 Chapter 2 — Instructions: Language of the Computer — 28

EOR Operations n Differencing operation n Set some bits to 1, leave others unchanged EOR X 9, X 10, X 12 // NOT operation X 10 00000000 000000001101 11000000 X 12 11111111 11111111 X 9 1111 0011111111 111111110010 Chapter 2 — Instructions: Language of the Computer — 29

n Branch to a labeled instruction if a condition is true n n CBZ register, L 1 n n if (register == 0) branch to instruction labeled L 1; CBNZ register, L 1 n n Otherwise, continue sequentially § 2. 7 Instructions for Making Decisions Conditional Operations if (register != 0) branch to instruction labeled L 1; B L 1 n branch unconditionally to instruction labeled L 1; Chapter 2 — Instructions: Language of the Computer — 30

Compiling If Statements n C code: if (i==j) f = g+h; else f = g-h; n n f, g, … in X 22, X 23, … Compiled LEGv 8 code: SUB X 9, X 22, X 23 CBNZ X 9, Else ADD X 19, X 20, X 21 B Exit Else: SUB X 9, X 22, x 23 Exit: … Assembler calculates addresses Chapter 2 — Instructions: Language of the Computer — 31

Compiling Loop Statements n C code: while (save[i] == k) i += 1; n n i in x 22, k in x 24, address of save in x 25 Compiled LEGv 8 code: Loop: LSL ADD LDUR SUB CBNZ ADDI B Exit: … X 10, X 22, #3 X 10, X 25 X 9, [X 10, #0] X 11, X 9, X 24 X 11, Exit X 22, #1 Loop Chapter 2 — Instructions: Language of the Computer — 32

Basic Blocks n A basic block is a sequence of instructions with n n No embedded branches (except at end) No branch targets (except at beginning) n n A compiler identifies basic blocks for optimization An advanced processor can accelerate execution of basic blocks Chapter 2 — Instructions: Language of the Computer — 33

More Conditional Operations n Condition codes, set from arithmetic instruction with Ssuffix (ADDS, ADDIS, ANDIS, SUBIS) n n negative (N): result had 1 in MSB zero (Z): result was 0 overlow (V): result overflowed carry (C): result had carryout from MSB Use subtract to set flags, then conditionally branch: n n n n B. EQ B. NE B. LT (less than, signed), B. LO (less than, unsigned) B. LE (less than or equal, signed), B. LS (less than or equal, unsigned) B. GT (greater than, signed), B. HI (greater than, unsigned) B. GE (greater than or equal, signed), B. HS (greater than or equal, unsigned) Chapter 2 — Instructions: Language of the Computer — 34

Conditional Example n if (a > b) a += 1; n a in X 22, b in X 23 SUBS X 9, X 22, X 23 // use subtract to make comparison B. LTE Exit // conditional branch ADDI X 22, #1 Exit: Chapter 2 — Instructions: Language of the Computer — 35

Signed vs. Unsigned n n n Signed comparison Unsigned comparison Example n n n X 22 = 1111 1111 X 23 = 0000 0000 0001 X 22 < X 23 # signed n n – 1 < +1 X 22 > X 23 # unsigned n +4, 294, 967, 295 > +1 Chapter 2 — Instructions: Language of the Computer — 36

n Steps required 1. 2. 3. 4. 5. 6. Place parameters in registers X 0 to X 7 Transfer control to procedure Acquire storage for procedure Perform procedure’s operations Place result in register for caller Return to place of call (address in X 30) § 2. 8 Supporting Procedures in Computer Hardware Procedure Calling Chapter 2 — Instructions: Language of the Computer — 37

Procedure Call Instructions n Procedure call: jump and link BL Procedure. Label n Address of following instruction put in X 30 n Jumps to target address n Procedure return: jump register BR LR n Copies LR to program counter n Can also be used for computed jumps n e. g. , for case/switch statements Chapter 2 — Instructions: Language of the Computer — 38

Leaf Procedure Example n C code: long int leaf_example (long int g, long int h, long int i, long int j) { long int f; f = (g + h) - (i + j); return f; } n Arguments g, …, j in X 0, …, X 3 n f in X 19 (hence, need to save $s 0 on stack) Chapter 2 — Instructions: Language of the Computer — 39

Leaf Procedure Example n LEGv 8 code: leaf_example: SUBI SP, #24 STUR X 10, [SP, #16] STUR X 9, [SP, #8] STUR X 19, [SP, #0] ADD X 9, X 0, X 1 ADD X 10, X 2, X 3 SUB X 19, X 10 ADD X 0, X 19, XZR LDUR X 10, [SP, #16] LDUR X 9, [SP, #8] LDUR X 19, [SP, #0] ADDI SP, #24 BR LR Save X 10, X 9, X 19 on stack X 9 = g + h X 10 = i + j f = X 9 – X 10 copy f to return register Resore X 10, X 9, X 19 from stack Return to caller Chapter 2 — Instructions: Language of the Computer — 40

Local Data on the Stack Chapter 2 — Instructions: Language of the Computer — 41

Register Usage n X 9 to X 17: temporary registers n n Not preserved by the callee X 19 to X 28: saved registers n If used, the callee saves and restores them Chapter 2 — Instructions: Language of the Computer — 42

Non-Leaf Procedures n n Procedures that call other procedures For nested call, caller needs to save on the stack: n n n Its return address Any arguments and temporaries needed after the call Restore from the stack after the call Chapter 2 — Instructions: Language of the Computer — 43

Non-Leaf Procedure Example n C code: int fact (int n) { if (n < 1) return f; else return n * fact(n - 1); } n n Argument n in X 0 Result in X 1 Chapter 2 — Instructions: Language of the Computer — 44

Leaf Procedure Example n LEGv 8 code: fact: SUBI SP, #16 STUR LR, [SP, #8] STUR X 0, [SP, #0] SUBIS XZR, X 0, #1 B. GE L 1 ADDI X 1, XZR, #1 ADDI SP, #16 BR LR L 1: SUBI X 0, #1 BL fact LDUR X 0, [SP, #0] LDUR LR, [SP, #8] ADDI SP, #16 MUL X 1, X 0, X 1 BR LR Save return address and n on stack compare n and 1 if n >= 1, go to L 1 Else, set return value to 1 Pop stack, don’t bother restoring values Return n=n-1 call fact(n-1) Restore caller’s n Restore caller’s return address Pop stack return n * fact(n-1) return Chapter 2 — Instructions: Language of the Computer — 45

Memory Layout n n Text: program code Static data: global variables n n Dynamic data: heap n n e. g. , static variables in C, constant arrays and strings E. g. , malloc in C, new in Java Stack: automatic storage Chapter 2 — Instructions: Language of the Computer — 46

n Byte-encoded character sets n ASCII: 128 characters n n Latin-1: 256 characters n n 95 graphic, 33 control ASCII, +96 more graphic characters § 2. 9 Communicating with People Character Data Unicode: 32 -bit character set n n n Used in Java, C++ wide characters, … Most of the world’s alphabets, plus symbols UTF-8, UTF-16: variable-length encodings Chapter 2 — Instructions: Language of the Computer — 47

Byte/Halfword Operations n LEGv 8 byte/halfword load/store n Load byte: n n n Store byte: n n n STURB Rt, [Rn, offset] Store just rightmost byte Load halfword: n n n LDURB Rt, [Rn, offset] Sign extend to 32 bits in rt LDURH Rt, [Rn, offset] Sign extend to 32 bits in rt Store halfword: n n STURH Rt, [Rn, offset] Store just rightmost halfword Chapter 2 — Instructions: Language of the Computer — 48

String Copy Example n C code: Null-terminated string void strcpy (char x[], char y[]) { size_t i; i = 0; while ((x[i]=y[i])!='') i += 1; } n Chapter 2 — Instructions: Language of the Computer — 49

String Copy Example n LEGv 8 code: strcpy: SUBI SP, 8 STUR X 19, [SP, #0] ADD X 19, XZR L 1: ADD X 10, X 19, X 1 LDURB X 11, [X 10, #0] ADD X 12, X 19, X 0 STURB X 11, [X 12, #0] CBZ X 11, L 2 ADDI X 19, #1 B L 1 L 2: LDUR X 19, [SP, #0] ADDI SP, 8 BR LR // push X 19 // // // i=0 X 10 = addr of y[i] X 11 = y[i] X 12 = addr of x[i] = y[i] if y[i] == 0 then exit i = i + 1 next iteration of loop restore saved $s 0 pop 1 item from stack and return Chapter 2 — Instructions: Language of the Computer — 50

n Most constants are small n n 12 -bit immediate is sufficient For the occasional 32 -bit constant MOVZ: MOVK: n move wide with zeros move with keep Use with flexible second operand (shift) MOVZ X 9, 255, LSL 16 0000 0000 0000 1111 0000 MOVK X 9, 255, LSL 0 0000 0000 0000 1111 § 2. 10 LEGv 8 Addressing for 32 -Bit Immediates and Addresses 32 -bit Constants Chapter 2 — Instructions: Language of the Computer — 51

Branch Addressing n B-type (Note, PC-relative, different from Jump) n B 1000 // go to location 10000 ten 5 6 bits n 26 bits CB-type n n 10000 ten CBNZ X 19, Exit // go to Exit if X 19 != 0 181 Exit 19 8 bits 19 bits 5 bits Both addresses are PC-relative (No PC+4 as in MIPS!) n Address = PC + offset (from instruction) Chapter 2 — Instructions: Language of the Computer — 52

LEGv 8 Addressing Summary Chapter 2 — Instructions: Language of the Computer — 53

LEGv 8 Encoding Summary Chapter 2 — Instructions: Language of the Computer — 54

n Two processors sharing an area of memory n n P 1 writes, then P 2 reads Data race if P 1 and P 2 don’t synchronize n n Hardware support required n n n Result depends of order of accesses Atomic read/write memory operation No other access to the location allowed between the read and write Could be a single instruction n n E. g. , atomic swap of register ↔ memory Or an atomic pair of instructions § 2. 11 Parallelism and Instructions: Synchronization Chapter 2 — Instructions: Language of the Computer — 55

Synchronization in LEGv 8 n n n Load exclusive register: LDXR Store exclusive register: STXR To use: n n n Execute LDXR then STXR with same address If there is an intervening change to the address, store fails (communicated with additional output register) Only use register instruction in between Chapter 2 — Instructions: Language of the Computer — 56

Synchronization in LEGv 8 Example 1: atomic swap (to test/set lock variable) n again: LDXR X 10, [X 20, #0] STXR X 23, X 9, [X 20] // X 9 = status CBNZ X 9, again ADD X 23, XZR, X 10 // X 23 = loaded value Example 2: lock n ADDI again: LDXR CBNZ STXR BNEZ n X 11, XZR, #1 X 10, [X 20, #0] X 10, again X 11, X 9, [X 20] X 9, again // // // copy locked value read lock check if it is 0 yet attempt to store branch if fails Unlock: STUR XZR, [X 20, #0] // free lock Chapter 2 — Instructions: Language of the Computer — 57

Many compilers produce object modules directly Static linking § 2. 12 Translating and Starting a Program Translation and Startup Chapter 2 — Instructions: Language of the Computer — 58

Producing an Object Module n n Assembler (or compiler) translates program into machine instructions Provides information for building a complete program from the pieces n n n Header: described contents of object module Text segment: translated instructions Static data segment: data allocated for the life of the program Relocation info: for contents that depend on absolute location of loaded program Symbol table: global definitions and external refs Debug info: for associating with source code Chapter 2 — Instructions: Language of the Computer — 59

Linking Object Modules n Produces an executable image 1. Merges segments 2. Resolve labels (determine their addresses) 3. Patch location-dependent and external refs n Could leave location dependencies for fixing by a relocating loader n n But with virtual memory, no need to do this Program can be loaded into absolute location in virtual memory space Chapter 2 — Instructions: Language of the Computer — 60

Loading a Program n Load from image file on disk into memory 1. Read header to determine segment sizes 2. Create virtual address space 3. Copy text and initialized data into memory n Or set page table entries so they can be faulted in 4. Set up arguments on stack 5. Initialize registers (including SP, FP) 6. Jump to startup routine n n Copies arguments to X 0, … and calls main When main returns, do exit syscall Chapter 2 — Instructions: Language of the Computer — 61

Dynamic Linking n Only link/load library procedure when it is called n n n Requires procedure code to be relocatable Avoids image bloat caused by static linking of all (transitively) referenced libraries Automatically picks up new library versions Chapter 2 — Instructions: Language of the Computer — 62

Lazy Linkage Indirection table Stub: Loads routine ID, Jump to linker/loader Linker/loader code Dynamically mapped code Chapter 2 — Instructions: Language of the Computer — 63

Starting Java Applications Simple portable instruction set for the JVM Compiles bytecodes of “hot” methods into native code for host machine Interprets bytecodes Chapter 2 — Instructions: Language of the Computer — 64

n n Illustrates use of assembly instructions for a C bubble sort function Swap procedure (leaf) n void swap(long int v[], long int k) { long int temp; temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; } v in X 0, k in X 1, temp in X 9 § 2. 13 A C Sort Example to Put It All Together C Sort Example Chapter 2 — Instructions: Language of the Computer — 65

The Procedure Swap swap: LSL X 10, X 1, #3 ADD X 10, X 10 LDUR X 9, [X 10, #0] LDUR X 11, [X 10, #8] STUR X 11, [X 10, #0] STUR X 9, [X 10, #8] BR LR // // X 10 = k * 8 X 10 = address of v[k] X 9 = v[k] X 11 = v[k+1] v[k] = X 11 (v[k+1]) v[k+1] = X 9 (v[k]) return to calling routine Chapter 2 — Instructions: Language of the Computer — 66

The Sort Procedure in C n Non-leaf (calls swap) n void sort (long int v[], size_t n) { size_t i, j; for (i = 0; i < n; i += 1) { for (j = i – 1; j >= 0 && v[j] > v[j + 1]; j -= 1) { swap(v, j); } } } v in X 0, n in X 1, i in X 19, j in X 20 Chapter 2 — Instructions: Language of the Computer — 67

The Outer Loop n Skeleton of outer loop: n for (i = 0; i <n; i += 1) { MOV X 19, XZR for 1 tst: CMP X 19, X 1 B. GE exit 1 // i = 0 // compare X 19 to X 1 (i to n) // go to exit 1 if X 19 ≥ X 1 (i≥n) (body of outer for-loop) ADDI X 19, #1 B for 1 tst exit 1: // i += 1 // branch to test of outer loop Chapter 2 — Instructions: Language of the Computer — 68

The Inner Loop n Skeleton of inner loop: n for (j = i − 1; j >= 0 && v[j] > v[j + 1]; j − = 1) { SUBI X 20, X 19, #1 for 2 tst: CMP X 20, XZR B. LT exit 2 LSL X 10, X 20, #3 ADD X 11, X 0, X 10 LDUR X 12, [X 11, #0] LDUR X 13, [X 11, #8] CMP X 12, X 13 B. LE exit 2 MOV X 0, X 21 MOV X 1, X 20 BL swap SUBI X 20, #1 B for 2 tst exit 2: // // // // j = i - 1 compare X 20 to 0 (j to 0) go to exit 2 if X 20 < 0 (j < 0) reg X 10 = j * 8 reg X 11 = v + (j * 8) reg X 12 = v[j] reg X 13 = v[j + 1] compare X 12 to X 13 go to exit 2 if X 12 ≤ X 13 first swap parameter is v second swap parameter is j call swap j –= 1 branch to test of inner loop Chapter 2 — Instructions: Language of the Computer — 69

Preserving Registers n Preserve saved registers: SUBI SP, #40 STUR LR, [SP, #32] STUR X 22, [SP, #24] STUR X 21, [SP, #16] STUR X 20, [SP, #8] STUR X 19, [SP, #0] MOV X 21, X 0 MOV X 22, X 1 n // // make save save copy room on stack for 5 regs LR on stack X 22 on stack X 21 on stack X 20 on stack X 19 on stack parameter X 0 into X 21 parameter X 1 into X 22 Restore saved registers: exit 1: LDUR X 19, [SP, #0] // restore X 19 from stack LDUR X 20, [SP, #8] // restore X 20 from stack LDUR X 21, [SP, #16] // restore X 21 from stack LDUR X 22, [SP, #24] // restore X 22 from stack LDUR X 30, [SP, #32] // restore LR from stack SUBI SP, #40 // restore stack pointer Chapter 2 — Instructions: Language of the Computer — 70

Effect of Compiler Optimization Compiled with gcc for Pentium 4 under Linux Chapter 2 — Instructions: Language of the Computer — 71

Effect of Language and Algorithm Chapter 2 — Instructions: Language of the Computer — 72

Lessons Learnt n n n Instruction count and CPI are not good performance indicators in isolation Compiler optimizations are sensitive to the algorithm Java/JIT compiled code is significantly faster than JVM interpreted n n Comparable to optimized C in some cases Nothing can fix a dumb algorithm! Chapter 2 — Instructions: Language of the Computer — 73

n Array indexing involves n n n Multiplying index by element size Adding to array base address Pointers correspond directly to memory addresses n § 2. 14 Arrays versus Pointers Arrays vs. Pointers Can avoid indexing complexity Chapter 2 — Instructions: Language of the Computer — 74

Example: Clearing an Array clear 1(int array[], int size) { int i; for (i = 0; i < size; i += 1) array[i] = 0; } clear 2(int *array, int size) { int *p; for (p = &array[0]; p < &array[size]; p = p + 1) *p = 0; } MOV X 9, XZR // i = 0 loop 1: LSL X 10, X 9, #3 // X 10 = i * 8 ADD X 11, X 0, X 10 // X 11 = address // of array[i] STUR XZR, [X 11, #0] // array[i] = 0 ADDI X 9, #1 // i = i + 1 CMP X 9, X 1 // compare i to // size B. LT loop 1 // if (i < size) // go to loop 1 MOV X 9, X 0 // p = address of // array[0] LSL X 10, X 1, #3 // X 10 = size * 8 ADD X 11, X 0, X 10 // X 11 = address // of array[size] loop 2: STUR XZR, 0[X 9, #0] // Memory[p] = 0 ADDI X 9, #8 // p = p + 8 CMP X 9, X 11 // compare p to < // &array[size] B. LT loop 2 // if (p < // &array[size]) // go to loop 2 Chapter 2 — Instructions: Language of the Computer — 75

Comparison of Array vs. Ptr n n Multiply “strength reduced” to shift Array version requires shift to be inside loop n n n Part of index calculation for incremented i c. f. incrementing pointer Compiler can achieve same effect as manual use of pointers n n Induction variable elimination Better to make program clearer and safer Chapter 2 — Instructions: Language of the Computer — 76

n n ARM: the most popular embedded core Similar basic set of instructions to MIPS ARM MIPS 1985 Instruction size 32 bits Address space 32 -bit flat Data alignment Aligned 9 3 15 × 32 -bit 31 × 32 -bit Memory mapped Date announced Data addressing modes Registers Input/output § 2. 16 Real Stuff: ARM Instructions ARM & MIPS Similarities Chapter 2 — Instructions: Language of the Computer — 77

Instruction Encoding Chapter 2 — Instructions: Language of the Computer — 78

n Evolution with backward compatibility n 8080 (1974): 8 -bit microprocessor n n 8086 (1978): 16 -bit extension to 8080 n n Adds FP instructions and register stack 80286 (1982): 24 -bit addresses, MMU n n Complex instruction set (CISC) 8087 (1980): floating-point coprocessor n n Accumulator, plus 3 index-register pairs § 2. 17 Real Stuff: x 86 Instructions The Intel x 86 ISA Segmented memory mapping and protection 80386 (1985): 32 -bit extension (now IA-32) n n Additional addressing modes and operations Paged memory mapping as well as segments Chapter 2 — Instructions: Language of the Computer — 79

The Intel x 86 ISA n Further evolution… n i 486 (1989): pipelined, on-chip caches and FPU n n Pentium (1993): superscalar, 64 -bit datapath n n n New microarchitecture (see Colwell, The Pentium Chronicles) Pentium III (1999) n n Later versions added MMX (Multi-Media e. Xtension) instructions The infamous FDIV bug Pentium Pro (1995), Pentium II (1997) n n Compatible competitors: AMD, Cyrix, … Added SSE (Streaming SIMD Extensions) and associated registers Pentium 4 (2001) n n New microarchitecture Added SSE 2 instructions Chapter 2 — Instructions: Language of the Computer — 80

The Intel x 86 ISA n And further… n n AMD 64 (2003): extended architecture to 64 bits EM 64 T – Extended Memory 64 Technology (2004) n n n Intel Core (2006) n n Intel declined to follow, instead… Advanced Vector Extension (announced 2008) n n Added SSE 4 instructions, virtual machine support AMD 64 (announced 2007): SSE 5 instructions n n AMD 64 adopted by Intel (with refinements) Added SSE 3 instructions Longer SSE registers, more instructions If Intel didn’t extend with compatibility, its competitors would! n Technical elegance ≠ market success Chapter 2 — Instructions: Language of the Computer — 81

Basic x 86 Registers Chapter 2 — Instructions: Language of the Computer — 82

Basic x 86 Addressing Modes n n Two operands per instruction Source/dest operand Second source operand Register Immediate Register Memory Immediate Memory addressing modes n n Address in register Address = Rbase + displacement Address = Rbase + 2 scale × Rindex (scale = 0, 1, 2, or 3) Address = Rbase + 2 scale × Rindex + displacement Chapter 2 — Instructions: Language of the Computer — 83

x 86 Instruction Encoding n Variable length encoding n n Postfix bytes specify addressing mode Prefix bytes modify operation n Operand length, repetition, locking, … Chapter 2 — Instructions: Language of the Computer — 84

Implementing IA-32 n Complex instruction set makes implementation difficult n Hardware translates instructions to simpler microoperations n n n Simple instructions: 1– 1 Complex instructions: 1–many Microengine similar to RISC Market share makes this economically viable Comparable performance to RISC n Compilers avoid complex instructions Chapter 2 — Instructions: Language of the Computer — 85

n Powerful instruction higher performance n n Fewer instructions required But complex instructions are hard to implement n n n May slow down all instructions, including simple ones § 2. 19 Fallacies and Pitfalls Fallacies Compilers are good at making fast code from simple instructions Use assembly code for high performance n n But modern compilers are better at dealing with modern processors More lines of code more errors and less productivity Chapter 2 — Instructions: Language of the Computer — 86

Fallacies n Backward compatibility instruction set doesn’t change n But they do accrete more instructions x 86 instruction set Chapter 2 — Instructions: Language of the Computer — 87

Pitfalls n Sequential words are not at sequential addresses n n Increment by 4, not by 1! Keeping a pointer to an automatic variable after procedure returns n n e. g. , passing pointer back via an argument Pointer becomes invalid when stack popped Chapter 2 — Instructions: Language of the Computer — 88

n Design principles 1. 2. 3. 4. n Layers of software/hardware n n Simplicity favors regularity Smaller is faster Make the common case fast Good design demands good compromises § 2. 20 Concluding Remarks Compiler, assembler, hardware LEGv 8: typical of RISC ISAs n c. f. x 86 Chapter 2 — Instructions: Language of the Computer — 89

Concluding Remarks n Additional ARMv 8 features: n n n Flexible second operand Additional addressing modes Conditional instructions (e. g. CSET, CINC) Chapter 2 — Instructions: Language of the Computer — 90