Arithmetic and Logic Chapter 5 www Nicer Land

Arithmetic and Logic Chapter 5 www. Nicer. Land. com www. Micro. Digital. Ed. com

Objectives • The concept of signed numbers and 2’complement • Addition and subtraction instructions • Carry and overflow • Logical instruction and masking • Compare instruction and branching • Shift, Rotate and Data serialization • BCD, Packed BCD and ASCII conversion. 2

Some ideas • 100 – 34 = ? • 99 – 34 = ? • 100 – 34 = (99 -34) + 1 • 34 – 19 = ? • 34 +100 -19 – 100 = 34 + (99 -19)+1 -100 3

• 10000 – 00101101 = ? • =01111 – 00101101 + 1 =A • 010110110 – 00101101 = • 010110110 + A – 10000 = 4

ADD instruction ADD Rd, Rr ; Rd = Rd + Rr ( Direct or immediate are not supported) Show the flag register is affected by the following instructions. LDI ADD R 21, 0 x. F 5 ; R 21 = F 5 H R 22, 0 x 0 B ; R 22 = 0 x 0 BH R 21, R 22 ; R 21 = R 21+R 22 = F 5+0 B = 00 and C = 1 F 5 H + 0 BH 100 H 1111 0101 + 0000 1011 0000 Solution: After the addition, register R 21 contains 00 and the flags are as follows: C = 1 because there is a carry out from D 7. Z = 1 because the result in destination register (R 21) is zero. H = 1 because there is a carry from D 3 to D 4. 5

ADD instruction ADD Rd, Rr ; Rd = Rd + Rr ( Direct or immediate are not supported) Assume that RAM location 400 H has the value of 33 H. Write a program to find the sum of location 400 H of RAM and 55 H. At the end of the program, R 21 should contain the sum. Solution: LDS LDI ADD R 2, 0 x 400 ; R 2 = 33 H (location 0 x 400 of RAM) R 21, 0 x 55 ; R 21 = 55 R 21, R 2 ; R 21 = R 21 + R 2 = 55 H + 33 H = 88 H, C = 0 6

ADC instructions + Write a program to add two 16 -bit numbers. The numbers are 3 CE 7 H and 3 B 8 DH. Place the sum in R 3 and R 4; R 3 should have the lower byte. Solution: ; R 2: R 1 = 3 B 8 D ; R 4: R 3 = 3 C E 7 ADD ADC R 3, R 1 R 4, R 2 ; R 3 = R 3 + R 1 = E 7 + 8 D = 74 and C = 1 ; R 4 = R 4 + R 2 + carry, adding the upper byte ; with carry from lower byte ; R 4 = 3 C + 3 B + 1 = 78 H (all in hex) Notice the use of ADD for the lower byte and ADC for the higher byte. 7

SUB instructions SUBI Rd, Rr Rd, K ; Rd = Rd – Rr ; Rd = Rd – K (immediate values are not supported) Show the steps involved in the following. LDI SUB R 20, 0 x 23 R 21, 0 x 3 F R 21, R 20 R 21 - R 20 = 3 F 0011 1111 = 23 0010 0011 1 C ; load 23 H into R 20 ; load 3 FH into R 21 ; R 21 <- R 21 -R 20 Solution: 0011 1111 + 1101 (2’s complement) 1 0001 1100 C = 0, D 7 = N = 0 (result is positive) The flags would be set as follows: N = 0, C = 0. (Notice that there is a carry but C = 0. We will discuss this more in the next section. ) The programmer must look at the N (or C) flag to determine if the result is positive or negative. 8

SBC instruction SBCI Rd, Rr ; Rd = Rd – Rr – C ; Rd = Rd – K – C ( immediate are not supported) 27 62 (H) - 11 96 (H) -------11 CC (H) ; R 26 = (62) ; R 27 = (27) LDI SUB R 28, 0 x 96 R 29, 0 x 12 R 26, R 28 SBC R 27, R 29 ; load the low byte (R 28 = 96 H) ; load the high byte (R 29 = 12 H) ; R 26 = R 26 - R 28 = 62 - 96 = CCH ; C = borrow = 1, N = 1 ; R 27 = R 27 - R 29 - C ; R 27 = 27 - 12 - 1 = 14 H After the SUB, R 26 has = 62 H - 96 H = CCH and the carry flag is set to 1, indicating there is a borrow (notice, N = 1). Because C = 1, when SBC is executed R 27 has 27 H - 12 H - 1 = 14 H. Therefore, we have 2762 H - 1296 H = 14 CCH. 9

Multiplication and Division Multiplication: Division: . DEF L 1: NUM = R 20 DENOMINATOR = R 21 QUOTIENT = R 22 LDI CLR NUM, 95 ; NUM = 95 DENOMINATOR, 10 ; DENOMINATOR = 10 QUOTIENT ; QUOTIENT = 0 INC SUB BRCC QUOTIENT NUM, DENOMINATOR L 1 ; branch if C is zero DEC ADD QUOTIENT NUM, DENOMINATOR ; once too many ; add back to it 10

Logic Instructions AND OR EOR COM NEG • • Rd, Rr Rd, Rr ; Rd = Rd AND Rr ; Rd = Rd OR Rr ; Rd = Rd XOR Rr ( immediate are not supported) ; Rd = 1’ Complement of Rd (1111 – Rd) ; Rd = 2’ Complement of Rd (10000 – Rd) AND is used to clear an specific bit/s of a byte OR is used to set an specific bit/s of a byte Show the results of the following. LDI R 20, 0 x 35 ANDI R 20, 0 x 0 F ; R 20 = 35 H ; R 20 = R 20 AND 0 FH (now R 20 = 05) Solution: AND 35 H 0 FH 05 H 0011 0101 0000 1111 0000 0101 ; 35 H AND 0 FH = 05 H, Z = 0, N = 0 11

Setting and Clearing bits AND OR EOR COM NEG • • AND Rd, Rr Rd, Rr ; Rd = Rd AND Rr ; Rd = Rd OR Rr ; Rd = Rd XOR Rr ( immediate are not supported) ; Rd = 1’ Complement of Rd (1111 – Rd) ; Rd = 2’ Complement of Rd (10000 – Rd) AND is used to clear an specific bit/s of a byte OR is used to set an specific bit/s of a byte OR 12

Branch and CP Instructions CP Rd, Rr • • ; Rd – Rr (only flags are set) BRVC is used to branch when o. Verflow is clear to zero BRVS is used to branch when o. Verflow is set to one 13

ROR instruction ROR Rd ; Rotate Right In ROR, as bits are rotated from left to right, the carry flag enters the MSB and the LSB exits to the carry flag. In other words, in ROR the C is moved to the MSB, and the LSB is moved to the C. See what happens to 0010 0110 after running 3 ROR instructions: CLC LDI ROR ROR R 20 , 0 x 26 R 20 ; make C = 0 (carry is 0 ) ; R 20 = 0010 0110 ; R 20 = 0001 0011 C = 0 ; R 20 = 0000 1001 C = 1 ; R 20 = 1000 0100 C = 1 14

ROL instruction ROL Rd ; Rotate Left In ROL, as bits are shifted from right to left, the carry flag enters the LSB and the MSB exits to the carry flag. In other words, in ROL the C is moved to the LSB, and the MSB is moved to the C. SEC LDI R 20, 0 x 15 ROL R 20 ; make C = 1 ; R 20 = 0001 0101 ; R 20 = 0010 1011 C = 0 ; R 20 = 0101 0110 C = 0 ; R 20 = 1010 1100 C = 0 ; R 20 = 0101 1000 C = 1 15

LSL instruction LSL Rd ; Logical Shift Left In LSL, as bits are shifted from right to left, 0 enters the LSB and the MSB exits to the carry flag. In other words, in LSL 0 is moved to the LSB, and the MSB is moved to the C. this instruction multiplies content of the register by 2 assuming that after LSL the carry flag is not set. In the next code you can see what happens to 00100110 after running 3 LSL instructions. CLC ; make C = 0 LDI R 20 , 0 x 26 ; R 20 = 0010 0110(38) c = 0 LSL R 20 ; R 20 = 0100 1100(74) C = 0 LSL R 20 ; R 20 = 1001 1000(148) C = 0 LSL R 20 ; R 20 = 0011 0000(98) C = 1; since C=1, content of R 20 ; is not multiplied by 2 16

LSR instruction LSR Rd ; Logical Shift Right In LSR, as bits are shifted from left to right, 0 enters the MSB and the LSB exits to the carry flag. In other words, in LSR 0 is moved to the MSB, and the LSB is moved to the C. this instruction divides content of the register by 2 and carry flag contains the remainder of division. In the next code you can see what happens to 0010 0110 after running 3 LSR instructions. LDI R 20, 0 x 26 LSR R 20 ; R 20 = 0010 0110 (38) ; R 20 = 0001 0011 (19) C = 0 ; R 20 = 0000 1001 (9) C = 1 ; R 20 = 0000 0100 (4) C = 1 17

ASR Instruction ASR Rd ; Arithmetic Shift Right ASR means arithmetic shift right. ASR instruction can divide signed number by 2. In ASR, as bits are shifted from left to right, MSB is held constant and the LSB exits to the carry flag. In other words MSB is not changed but is copied to D 6, D 6 is moved to D 5, D 5 is moved to D 4 and so on. In the next code you can see what happens to 0010 0110 after running 5 ASR instructions. LDI R 20, 0 x. D 0 ; R 20 = 1101 0000(-48) C = 0 ASR R 20 ; R 20 = 1110 1000(-24) C = 0 ASR R 20 ; R 20 = 1111 0100(-12) C = 0 ASR R 20 ; R 20 = 1111 1010(-6) C = 0 ASR R 20 ; R 20 = 1111 1101(-3) C = 0 ASR R 20 ; R 20 = 1111 1110(-1) C = 1 18

BCD, Packed BCD and ASCII conversion. • • ASCII BCD Codes Packed BCD 1 BCD 0 ASCII and BCD Codes for Digits 0– 9 19

Packed BCD to ASCII conversion To convert packed BCD to ASCII: • you must first convert it to unpacked BCD. • Then the unpacked BCD is tagged with 011 0000 (30 H). Packed BCD = 1001 0010 Un packed BCD = 0000 1001 , 0000 0010 ACSII = 0011 1001 , 0011 0010 20